MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 4

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
Pin Description
4
64 Pin
MQFP
20-27
2-11
12
13
14
15
16
17
18
19
28
29
30
31
32
1
-
Pin #
68 Pin
PLCC
25-26
27-36
46-53
37
38
39
40
41
42
43
44
45
54
55
56
57
58
AD0 - AD7 Data Bus (Bidirectional). These pins provide microprocessor access to the
R/W \ WR Read/Write \ Write (Input). In case of non-multiplexed and Motorola multiplexed
AS/ALE
A0 - A9
RxCEN
TxCEN
DS/RD
REOP
Name
TEOP
VSS5
VSS1
DTA
IRQ
NC
NC
CS
IM
No Connect. Ground
Address 0 - 9(Input). When non-multiplexed CPU bus is selected, these lines
provide the A0 - A9 address lines to IDX internal memories.
Data Strobe/Read (Input). For Motorola multiplexed bus operation, this active
high DS input works with CS to enable the read and write operations.
For Motorola non-multiplexed CPU bus operation, this input is DS. This active low
input works in conjunction with CS to enable the read and write operations.
For Intel/National multiplexed bus operations, this input is RD. This active low
input sets the data bus lines (AD0-AD7) as outputs.
buses, this input is Read/Write. This input controls the direction of the data bus
lines (AD0 - AD7) during a microprocessor access.
For Intel/National multiplexed bus, this input is WR. This active low signal
configures the data bus lines (AD0-AD7) as inputs.
Chip Select (Input). Active low input enabling a microprocessor read or write of
internal memories.
Address Strobe or Latch Enable (Input). This input is only used if multiplexed
bus is selected via IM input pin.
CPU Interface Mode (Input). If High, this input sets the device in the multiplexed
microprocessor mode. If this input is grounded, the device resumes non-
multiplexed CPU interface.
Data Acknowledgment (Open Drain Output). This active low output indicates
that a data bus transfer is complete. A 10Kohm pull-up resistor is required at this
output.
Interrupt Request Output (Open Drain Output). This active low output notifies
the controlling microprocessor of an interrupt request. It goes Low only when the
bits in the Interrupt Enable Register are programmed to acknowledge the source
of the interrupt as defined in the Interrupt Status Register.
No Connect. Ground
Ground.
internal memories. In the multiplexed bus mode, these pins also provide the input
address to the internal Address Latch circuit.
Ground.
Transmit End of Packet (Input). This is a strobe that is generated by the HDLC
controller chip for one bit period during the last bit of the closing flag of the
transmit packet.
Receive End of Packet (Input). A receive packet will normally be terminated
when the HDLC controller asserts the REOP strobe for one bit period, one bit time
after the closing flag is received.
Transmit Clock Enable (Output). The HDLC transmitter is controlled by the IDX-
generated Transmit Clock Enable signal, TxCEN.
Receive Clock Enable (Output). The HDLC receiver is controlled by the IDX-
generated Receive Clock Enable signal, RxCEN.
Description
Advance Information