MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 63

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MT90812

Manufacturer Part Number
MT90812
Description
Integrated Digital Switch (IDX)
Manufacturer
Mitel Networks Corporation
Datasheet

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Advance Information
22.8
The register is configured as follows:
A system write to the TX FIFO buffer is performed by addressing location 07
to 20-bytes can be written to the FIFO. The length of the message is determined by the number of bytes written
to the FIFO. The FSK output is memory mapped to address 5F
Refer to “Frequency Shift Keying (FSK) Transmitter” on page 45.
22.9
The register is configured as follows:
This register is a read only register. When a conference overflow occurs the Conference overflow bit in the
Interrupt register will be set and the conference ID will be stored in this register. The conference ID will be that
of the conference which had an accumulator overflow. The Conference ID corresponds to the Conference ID
numbers programmed in the Conference Party Control registers. Refer to Section 22.20.
The Conference ID in this register will not be updated again until it is reset. The register is reset following a
read of the register or resetting the conference block or MT90812 device.
Following an IRQ being asserted by the conference circuit, the INT would generally be read by the external uP.
Reading the Interrupt Status Register (INTS) will clear the Conference Overflow bit. Further conference
overflows do not trigger an interrupt until the conference overflow bit is cleared. The conference overflow
interrupt is maskable using the Interrupt Enable Register (INTE). The conference interrupt mask does not
disable updates of the CONFO register.
Write Address is: 007
Reset Value is: 00
Read Address is: 008
Reset Value is: 00
7-0
7-3
2-0
Bit
Bit
FSK Transmit Memory (FSKM)
Conference Overflow Status Register (CONFO)
unused
D7-D0
C2-C0
Name
Name
H
H
H
H
-
D7
TX FIFO buffer. D7 is the MSB.
Unused.
Conference ID number. Valid conference ID numbers are:
001 = conference 1
010 = conference 2
011 = conference 3
100 = conference 4
101 = conference 5
7
7
-
D6
6
6
-
D5
5
5
-
D4
4
4
-
D3
3
3
C2
D2
2
2
Description
Description
H
C1
as shown in Table 3 on page 14
D1
1
1
C0
0
D0
0
H
of the Control Register page. Up
MT90812
59

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