MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 51

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

Advance Information
•
•
•
18.0 Ringing Generator
A Ringing Generator is provided on pins R+ and R-. The output are two square waves 180 degrees out of
phase. The frequency is selected with bits F1,F0 in Ringer and FSK Control Register (RFC) and can be 16, 20,
25 or 50 Hz. Setting the bit RE to “0” in the same register tri-states the drivers for both pins R+ and R-.
19.0 Supervisory Signal Detection and Cadence Measurement
Two energy detect blocks, A and B, are provided for monitoring supervisory signalling during trunk calls. Each
of energy detect blocks can be assigned to an incoming channel, by programming one of the two Connect
Memory Low locations 70
and High Threshold Registers (EDLTA/B or EDHTA/B). The Energy Detect blocks are enabled by setting ENA
or ENB bits in the Tone Generation and Energy Detect Control Register (TEDC) described on page 61.
The energy detect is implemented using a peak detector with an exponential attack and decay time constant of
2 msec and a 25 msec “leaky” hold time to bridge between the envelope peaks. The peak detector decays
exponentially following the hold time limit.
Supervisory signalling cadence measurement is illustrated in Fig. 27. A counter is used to time the cadence of
the signal. When the signal envelope crosses the energy detect high threshold at point A, the counter value,t0,
is transferred to the SSCR register and the counter is reset and starts counting the next interval. The position
of the signal envelope, now above the high threshold, is indicated with bit 7 of SSCR (also labelled the P bit)
set to 1. An interrupt is generated and the energy detect bit in the Interrupt Status Register (INTS) is set.
At point B the low threshold limit is crossed, the SSCR register is updated with the new count, t1, and an
interrupt is generated. The position of the signal envelope, now below the low threshold, is indicated with the P
bit of SSCR set to 0.
Transmit Mark
Transmit Data Packet
End Transmission
3.
4.
5.
6.
7.
Subsequently the interrupt occur once every 8 bits (53 1/3 frames). Wait until the desired number of
channel seizure bits have been sent.
Switch to mark as the idle state. Again use end of transmission interrupt to count the number of
mark bits. When switching the idle state the interrupt bit count is not affected, i.e. the bit count is not
restarted but will interrupt 8 bit times after the last interrupt. Wait until the desired number of mark
bits have been sent.
Select FIFO empty interrupt. End of transmission interrupt is disabled by the selection. Even though
the FIFO is empty there will be no interrupt because the empty interrupt occurs only when the FIFO
is read to empty, not when it is emptied via FIFO clear. Write to FIFO for up to 20 bytes. The first
byte will be sent on the next bit boundary or the one after depending on when the byte is written.
When FIFO empty interrupts, reload FIFO. Repeat as necessary until the entire message has been
sent. When the FIFO empty interrupts, there are 11 bit times (73 1/3 frames) before idle state
transmission will commence.
After the FIFO has been loaded for the last time, switch to end of transmission interrupt. Select
mark as the idle state.
Wait for end of transmission interrupt which occurs after 2 idle state bits have been sent after the
stop bit of the last FIFO byte. If the system does not disable FSK via FEN=0, end of transmission
will interrupt again once every 8 bit times.
H
and 71
H
. A low and high threshold level is programmed in the Energy Detect Low
MT90812
47