S2078TB Applied Micro Circuits Corporation, S2078TB Datasheet - Page 5

• Manufacturer Part Number: S2078TB
• Description: DUAL FIBRE CHANNEL TRANSCEIVER
• Manufacturer: Applied Micro Circuits Corporation

TRANSMITTER DESCRIPTION
The transmitter section of the S2078 contains a
single PLL which is used to generate the serial rate
transmit clock for all transmitters. Transmitter
functionalities shown schematically in Figure 3. Two
channels are provided with a variety of options re-
garding input clocking and loopback. The transmit-
ters operate at 1.062 GHz, 10 or 20 times the
reference clock frequency.
Data Input
The S2078 has been designed to simplify the paral-
lel interface data transfer and provides flexibility in
the clocking of parallel data. Prior implementations
of this function have either forced the user to syn-
chronize transmit data to the reference clock or to
provide the output clock as a reference to the PLL,
resulting in increased jitter at the serial interface.
The S2078 incorporates a unique FIFO structure
which enables the user to provide a “clean” refer-
ence source for the PLL and to accept a separate
external clock which is used exclusively to reliably
clock data into the device.
The S2078 also provides a system clock output,
TCLKO, which is derived from the internal VCO. The
frequency of this output is constant at the parallel
word rate, 1/10 the serial data rate, regardless of
whether the reference is provided at 1/10 or 1/20 the
serial data rate. This clock can be used by upstream
circuitry as a system clock. See Table 1.
Table 1. Operating Rates
Note: SDR = Serial Data Rate.
Table 2. Input Modes
Note that internal synchronization of FIFOs is performed upon
de-assertion of RESET.
October 13, 2000 / Revision D
DUAL FIBRE CHANNEL TRANSCEIVER
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Data to be input to the S2078 should be coded to
insure transition density and DC balance. Data is input
to each channel of the S2078 as a 10 bit wide word. An
input FIFO and a clock input, TBCx, are provided for
each channel of the S2078. The device can operate in
two different modes. The S2078 can be configured to
use either the TBCx (TBC MODE) input or the
REFCLK input (REFCLK MODE). Table 2 provides a
summary of the input modes for the S2078.
Operation in the TBC MODE makes it easier for us-
ers to meet the relatively narrow setup and hold time
window required by the 106.25 Mbps 10 bit inter-
face. The TBC signal is used to clock the data into
an internal holding register and the S2078 synchro-
nizes its internal data flow to ensure stable opera-
tion. REFCLK, not TBCx, is used as the reference
for the transmit PLL. This ensures minimum jitter on
the high speed serial data stream.
The TBC must be frequency locked to REFCLK, but
may have an arbitrary but fixed phase relationship. Ad-
justment of internal timing of the S2078 is performed
during reset. Once synchronized, the S2078 can tolerate
up to 3ns of phase drift between TBC and REFCLK.
Figure 5 demonstrates the flexibility afforded by the
S2078. A low jitter reference is provided directly to
the S2078 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. This clock can be buffered as re-
quired without concern about added delay. There is
no phase requirement placed upon TCLKO and the
TBCx clock, which is provided back to the S2078,
Figure 5. DIN Clocking with TBC
ASIC
MAC
TCLKO
DINx[0:9]
TBCx
106.25 MHz or 53.125 MHz
OSCILLATOR
S2078
REFCLK
REF
PLL
S2078
5