IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 20

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

information and PFP buffer segment fill level.
4 document [Glossary].
DIP-2 error insertion
field in Table 97, SPI-4 ingress diagnostics register (register_offset 0x0F)
specifies the number of errors to be generated. A logic one written to
I_ERROR_INS will activate the I_DIP_E_NUM field and trigger error insertion.
The I_ERROR_INS field self clears when the number of errors have been
generated.
LVTTL and LVDS status interface selection
4. HIGH = LVDS status interface, LOW = LVTTL status interface.
3.2.2 SPI-4 egress
3.2.3 SPI-4 startup handshake
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
Out of synch, send status training
In synch, send status frame
In synch, send status frame
Out of synch, send status training
Out of synch, send status training
In synch, send status frame
In synch, send status frame
In synch, send status frame
Out of synch, send status training
In synch, send status frame
In synch, send status frame

The normal status information is generated based on ingress buffer full
For information on DIP-2 generation and training pattern refer to the OIF SPI-
A number of consecutive DIP-2 errors can be generated. The I_ DIP_E_NUM
The LVDS_STA pin selects which FIFO status interface is being used for SPI-
The SPI-4 egress includes





Normal status information when in the IN_SYNCH state
Status channel synchronization
Status updating
Data transfer
Periodic training
PFP interface
Ingress
Ingress
Ingress
Out of synch, send data training
In synch, send data/idle
Out of synch, send data training
In synch, send data/idle
Out of synch, send data training
Out of synch, send data training
In synch, send data/idle
Out of synch, send data training
In synch, send data/idle
Out of synch, send data training
Out of synch, send data training
egress
Egress
Egress
20
SPI-4 egress configurable parameters
Calendar and shadow calendar
(register_offset 0x00) bit for manual reconfiguration swap
Multiple burst enable
systems with long latency between updates.
SPI-4 egress LID to LP map
All parameters as listed in the 0IF SPI-4 document [see Glossary]
CALENDAR_LEN: 4 to 1,024 in increments of 4
CALENDAR_M: 1 to 256 in increments of 1
MaxBurst1 (MaxBurst_S): 16 to 256 in increments of 16
MaxBurst2 (MaxBurst_H): 16 to 256 in increments of 16
Alpha: 1 to 256 in increments of 1
DATA_MAX_T: 1 to 4,294,967,040 in increments of 1
FIFO_MAX_T: 1 to 16,777,215 in increments of 1
- 256 entries
- E_CSW_EN field in Table 104, SPI-4 egress configuration register_0
- Allows more than one burst to be sent to an LP. Feature included to relieve
- 256 entries, one per SPI-4 LP
- Enable bit
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006