IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 58

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

for odd or even parity. The PARITY_EN bit must be set for this to become
effective. Odd parity is standard for SPI-3 interfaces.
generation and checking, according to the state of the EVEN_PARITY bit.
watermark value. 0x10 is the highest watermark that can be set, meaning all
ingress buffers will be full before backpressure will be initiated on a SPI-3 ingress
interface. The WATERMARK field value of 0x08 is used to set the watermark
for a half-full ingress buffer before tripping backpressure. The units of WATER-
MARK are one-sixteenth of the available ingress buffering per unit. Each unit
is equal to 128 bytes. BACKPRESSURE_EN must be set [Register_offset 0x01]
for the watermark to become effective. The watermark field is usually set to 0x10,
and the FREE_SEGMENT field of Table 75, SPI-3 ingress port descriptor tables
(Block_base 0x1200) is used for per LID backpressure.
SPI-3 ingress configuration register (Block_base
0x0200 + Register_offset 0x01)
Each register has read and write access.
following paragraphs.
enabled or disabled. Disabling backpressure means that data coming into the
ingress may be lost if the SPI-3 interface ingress buffers overflow. The SPI-3
interface can run at full-rate, however, since there will be no backpressure.
Attached devices that do not respond properly to backpressure should be
interfaced by disabling backpressure.
ingress buffer fill level is equal to the WATERMARK value [Register_offset 0x00],
or the free segment buffer threshold Table 75, SPI-3 ingress port descriptor table
(Block_base 0x1200) has been reached for any active LID.
is useful when there is only one LP on an interface, such as with some single-
PHY devices.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
BACKPRESSURE_EN
FIX_LP
Reserved
EVEN_PARITY A SPI-3 interface is provisioned to generate and to check
PARITY_EN A SPI-3 interface is provisioned to enable or disable parity
WATERMARK A SPI-3 interface can be set to a SPI-3 ingress port
There is one register for SPI-3 ingress configuration per SPI-3 interface.
The bit fields for a SPI-3 ingress configuration register are described in the
BACKPRESSURE_EN
Enabling backpressure will cause the I_ENB signal to be asserted when the
FIX_LP
Field
0=Odd parity on this port
1=Even parity on this port
0=Disable parity on this SPI-3 port
1=Enable parity on this SPI-3 port
A SPI-3 interface can fix the logical port address to 0x00. This
0=Disable backpressure on this SPI-3 ingress.
1=Enable backpressure on this SPI-3 ingress interface.
0= Do not fix logical port address to 0x00, but use the actual
LP found in the packet fragments.
1= Fix logical port address to 0x00
A SPI-3 interface can have backpressure
Bits
31:2
1
0
Length
30
1
1
Initial Value
0x0000
0b1
0b0
58
SPI-3 ingress fill level register (Block_base 0x0200
+ Register_offset 0x02)
Each register has read-only access. The bit fields of a SPI-3 ingress fill level
register are described.
register, the value read from it will change rapidly and is used for internal
diagnostics only.
SPI-3 ingress max fill register (Block_base 0x0200
+ Register_offset 0x03)
interface. Each register has read-only access, and is cleared after reading.
0x10 is the highest filling level, meaning all ingress buffers had been full at some
time since the last read of the FILL_MAX field. The units of FILL_MAX are one-
sixteenth of the available ingress buffering. Each unit is equal to 128 bytes. The
bit field of a SPI-3 ingress max fill level register is described. The Table 53 - SPI-
3 ingress max fill level register (Register_offset=0x03) is for diagnostics only.
the SPI-3 ingress max fill level register.
9.3.3 Block base 0x0500 registers
SPI-3 egress LID to LP map (Block_base 0x0500 +
Register_offset 0x00-0x3F)
potential SPI-3 LID.
3 egress LID to LP maps are used to map SPI-3 egress logical identifiers to SPI-
3 logical port addresses that are in-band with the SPI-3 egress packet fragments.
as the register address.
LP
ENABLE
BIT_REVERSAL
There is one register for SPI-3 ingress fill level register per SPI-3 interface.
FILL_CUR
I_FCLK_AV Current SPI-3 ingress clock availability is checked here.
There is one register for SPI-3 ingress max fill level register per SPI-3
FILL_MAX Maximum SPI-3 ingress buffer fill level since the last read of
There are 64 SPI-3 egress LID to LP maps per SPI-3 interface, one per
The SPI-3 egress LID to LP maps have read and write access. The SPI-
LP
FILL_CUR
I_FCLK_AV
FILL_MAX
Field
Field
Field
The LP programmed is associated to the LID with the same number
Current SPI-3 ingress buffer fill level. Since this is a real-time
0=SPI-3 ingress clock not detected on a SPI-3 port
1=SPI-3 ingress clock transitions detected on a SPI-3 port
Bits
Bits
4:0
4:0
5
Bits
7:0
INDUSTRIAL TEMPERATURE RANGE
8
9
Length
Length
Length
1
5
5
8
1
1
Initial Value
Initial Value
APRIL 10, 2006
Initial Value
0x00
0x00
0b1
0x00
0b0
0b0