IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 67

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

9.3.14 Block base 0x1900 registers
SPI-4 to SPI-3 PFP register (Block_base 0x1900 +
Register_Offset 0x00)
at Block_Base 0x1900 + Register_offset 0x00. A SPI-4 to SPI-3 PFP Register
has read and write access. The bit fields of a SPI-4 to SPI-3 PFP Register are
described.
face that will ever be used is programmed into the NR_LID field. Once configured
after reset, this value can not be changed. Fewer LIDs can be used by not
activating some of the LIDs, but more LIDs than the value in NR_LID are not
allowed and will generate an error. The NR_LID field is important, as the buffer
segment pool is divided among the number of LIDs programmed into the
NR_LID field.
for a SPI-3 egress is available per SPI-3 physical port. A configurable part of
the buffer segment pool can be assigned to each of the LIDs, as determined by
the NR_LID value, per SPI-3 physical interface. The buffer size (M) for a LID
can be configured in multiples of 256 bytes. Modifications of the buffer size
allocated to a LID are supported only when the logical port associated to the LID
is disabled. Attempts to allocate more memory than available will generate an
allocation error event. The indirect access module will discard the attempt.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
The SPI-4 ingress to SPI-3 egress Packet Fragment Processor registers are
NR_LID
A 128 Kbyte SPI-4 to SPI-3 buffer segment pool for storing packet fragments
NR_LID
Reserved
Field
The maximum number of LIDs per SPI-3 physical inter-
Bits
2:0
7:3
Length
3
5
Initial Value
0b011
0x00
67
segments. Each buffer segment is equal to 256 bytes. The buffer segments are
shared among the number of logical ports defined by the static NR_LID
configuration. The buffer segments do not have to be equally shared among
the allocated LIDs. One buffer segment corresponds to a packet fragment to be
forwarded to a SPI-3 egress physical interface.
interface that will never have more than eight LIDs, set the NR_LID field for this
interface to 0x02. This allows 128 buffer segments for a LID with the total number
of buffer segments for all eight LIDs equal to 508.
Program field M for that LID to 0x018 (24 base 10). Let’s say you want to set
the per-LID starving backpressure for the SPI-4 ingress interface when 20 of
the 24 allocated buffers for this LID are full. In other words, you want to assert
SPI-4 ingress starving when only 4 segments remain for this LID. Since
M=0x018, N=1 from the description of the M field above [Block_base 0x1800].
Setting the FREE_SEGMENT_S field to 4 then yields the desired
THRESHOLD_S of 4. Similarly, to set the per-LID SPI-4 ingress hungry
threshold, THRESHOLD_H, to trip when only 6 buffer segments remain for this
LID, program the FREE_SEGMENT_H field for this LID to 6.
The 128 Kbyte SPI-4 to SPI-3 buffer segment pool is divided into 508 buffer
An example of the use of the buffer segment pool follows. For a SPI-3 egress
Let’s say you want only 24 (base 10) buffer segments for one of the LIDs.
NR_LID
0b000
0b001
0b010
0b011
0b100
0b101
Maximum Number
of LIDs
16
32
64
1
4
8
INDUSTRIAL TEMPERATURE RANGE
Maximum Buffer Segments
for a LID
508
256
128
64
32
16
APRIL 10, 2006