IDT88P8344 Integrated Device Technology, IDT88P8344 Datasheet - Page 71

• Manufacturer Part Number: IDT88P8344
• Description: Spi Exchange 4 X Spi-3 To Spi-4 Issue 1.0
• Manufacturer: Integrated Device Technology

SPI-4 ingress calendar configuration register
(Block_base 0x0300 + Register_offset 0x04 - 0x05)
0x0300 and have read and write access. The Register_offset for calendar_0
is 0x04. The Register_offset for calendar_1 is 0x05.
the Bridgeport calendar length has to be multiply of 4, and the calendar M is
programmable. Therefore, the user may need to add an FPGA between the
Bridgeport & the adjacent device SPI-4 status signals.
the calendar sequence is repeated before a DIP-2 parity and “1 1” framing
words are inserted. The actual calendar_M value used is one more than the
value programmed into the I_CAL_M field.
the SPI-4 ingress calendar. The actual length of the calendar is four times the
value of one more than the I_CAL_LEN field: (I_CAL_LEN + 1)*4. For example,
if the I_CAL_LEN field is programmed to 0x04, the actual value used is 0x14.
The calendar length must be at least as large as the number of active SPI-4
ingress LPs.
SPI-4 ingress watermark register (Block_base
0x0300 + Register_offset 0x06)
0x06. The SPI-4 ingress Watermark Register has read and write access. A SPI-
4 interface can be set to a Watermark Value per PFP. 0x1F is the highest
watermark that can be set, meaning all ingress buffers will be full before
backpressure will be initiated on a SPI-4 ingress interface PFP. A WATER-
MARK field value of 0x0F is used to set a watermark for a half-full ingress buffer
before tripping backpressure. The units of WATERMARK are one-thirty-
second of the available ingress buffering per unit. Each unit is equal to 128 bytes.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
WATERMARK
reserved
WATERMARK
reserved
WATERMARK 20:16
reserved
WATERMARK 28:24
reserved
The SPI-4 ingress calendar configuration registers are at Block_base
The bit fields of a SPI-4 ingress calendar configuration register are described.
Some devices have a fixed calendar length and a fixed calendar M, while
I_CAL_M
I_CAL_LEN
SPI-4 ingress Watermark Register is at Block_base 0x0300, Register_offset
I_CAL_M
I_CAL_LEN
Field
Field
The I_CAL_M value programmed defines the number of times
15:13
23:21
31:29
Bits
12:6
The I_CAL_LEN value programmed defines the length of
4:0
7:5
Length Initial Value
Bits
5
3
5
3
5
3
5
3
13:8
7:0
0x0D
0x0D
0x0D
0x0D
Length
0
0
0
0
8
6
Watermark for PFP A
Watermark for PFP B
Watermark for PFP C
Watermark for PFP D
Initial Value
Function
0x01
0
71
SPI-4 ingress fill level register (Block_base 0x0300
+ Register_offset 0x07-0x0A)
0x0300. Each register has read-only access.
Register_offset 0x07.
Register_offset 0x08.
Register_offset 0x09.
Register_offset 0x0A.
register, the value read from it will change rapidly and is used for internal
diagnostics only.
SPI-4 ingress max fill level register (Block_base
0x0300 + Register_offset 0x0B to 0x0E)
at Block_base 0x0300. Each register has read-only access, and is cleared after
reading. The value 0x20 is the highest filling level, meaning all ingress buffers
on a PFP had been full at some time since the last read of the FILL_MAX field.
The units of FILL_MAX are one-thirty-second of the available ingress buffering
per PFP. Each unit is equal to 128 bytes.
+ Register_offset 0x0B.
+ Register_offset 0x0C.
+ Register_offset 0x0D.
+ Register_offset 0x0E.
SPI-4 ingress max fill level register.
SPI-4 ingress diagnostics register (Block_base
0x0300 + Register_offset 0x0F)
I_FORCE_TRAIN
I_ERR_INS
I_DIP_NUM
There is one SPI-4 ingress fill level register per SPI-3 interface at Block_base
The SPI-4 ingress fill level register for PFP A is at Block_base 0x0300 +
The SPI-4 ingress fill level register for PFP B is at Block_base 0x0300 +
The SPI-4 ingress fill level register for PFP C is at Block_base 0x0300 +
The SPI-4 ingress fill level register for PFP D is at Block_base 0x0300 +
The bit field of a SPI-4 ingress fill level register is described.
FILL_CUR Current SPI-4 ingress buffer fill level. Since this is a real-time
There are four SPI-4 ingress max fill level registers, one per SPI-3 interface,
The SPI-4 ingress max fill level register for PFP A is at Block_base 0x0300
The SPI-4 ingress max fill level register for PFP B is at Block_base 0x0300
The SPI-4 ingress max fill level register for PFP C is at Block_base 0x0300
The SPI-4 ingress max fill level register for PFP D is at Block_base 0x0300
The bit field of a SPI-4 ingress max fill level register is described.
FILL_MAX Maximum SPI-4 ingress buffer fill level since the last read of the
FILL_CUR
FILL_MAX
Field
Field
Field
Bits
Bits
Bits
5:0
5:0
5:2
INDUSTRIAL TEMPERATURE RANGE
0
1
Length
Length
Length
6
6
1
1
4
APRIL 10, 2006
Initial Value
Initial Value
Initial Value
0x00
0x0
0
0
0