IDT72V205L15TF IDT, Integrated Device Technology Inc, IDT72V205L15TF Datasheet - Page 19

• Manufacturer Part Number: IDT72V205L15TF
• Description: IC FIFO SYNC 16KX9 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L15TF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72V205L15TF; 800-1510

NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. t
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
WCLK
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
RCLK
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
WCLK
RCLK
WEN
REN
PAF
WEN
REN
In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245.
In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245.
and the rising edge of WCLK is less than t
PAE
and the rising edge of RCLK is less than t
SKEW2
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK
D - (m + 1) Words in FIFO
t
t
CLKH
n words in FIFO
n + 1words in FIFO
CLKH
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
t
ENS
t
t
CLKL
t
SKEW2
CLKL
(2)
,
(4)
(3)
SKEW2
SKEW2
t
ENH
t
ENH
, then the PAE deassertion may be delayed one extra RCLK cycle.
, then the PAF deassertion time may be delayed an extra WCLK cycle.
t
PAES
t
PAFS
19
TM
n + 1 words in FIFO
n + 2 words in FIFO
D - m W
t
ENS
(2)
(3)
,
t
ENH
COMMERCIAL AND INDUSTRIAL
t
PAES
TEMPERATURE RANGES
OCTOBER 22, 2008
n Words in FIFO
n + 1 words in FIFO
4294 drw 22
(2)
,
(3)