IDT72V205L15TF IDT, Integrated Device Technology Inc, IDT72V205L15TF Datasheet - Page 9

• Manufacturer Part Number: IDT72V205L15TF
• Description: IC FIFO SYNC 16KX9 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L15TF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72V205L15TF; 800-1510

IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D
CONTROLS:
RESET (RS)
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Half-Full Flag (HF) and Programmable Almost-Full Flag (PAF) will
be reset to HIGH after t
be reset to LOW after t
Flag (EF) will reset to LOW in IDT Standard mode but will reset to HIGH in FWFT
mode. During reset, the output register is initialized to all zeros and the offset
registers are initialized to their default values.
WRITE CLOCK (WCLK)
(WCLK). Data setup and hold times must be met with respect to the LOW-to-HIGH
transition of WCLK.
WRITE ENABLE (WEN)
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
cycle.
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF flag is updated on the rising
edge of WCLK.
further write operations. Upon the completion of a valid read cycle, IR will go
LOW allowing a write to occur. The IR flag is updated on the rising edge of WCLK.
READ CLOCK (RCLK)
Clock (RCLK), when Output Enable (OE) is set LOW.
READ ENABLE (REN)
register on the rising edge of every RCLK cycle if the device is not empty.
no new data is loaded into the output register. The data outputs Q
the previous data value.
word written to an empty FIFO, must be requested using REN. When the last
word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting
further read operations. REN is ignored when the FIFO is empty. Once a write
is performed, EF will go HIGH allowing a read to occur. The EF flag is updated
on the rising edge of RCLK.
Data inputs for 18-bit wide data.
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
The Write and Read Clocks can be asynchronous or coincident.
When the WEN input is LOW, data may be loaded into the FIFO RAM array
When WEN is HIGH, no new data is written in the RAM array on each WCLK
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
The Write and Read Clocks can be asynchronous or coincident.
When Read Enable is LOW, data is loaded from the RAM array into the output
When the REN input is HIGH, the output register holds the previous data and
In the IDT Standard mode, every word accessed at Q
0
- D
17
)
RSF
RSF
. The Programmable Almost-Empty Flag (PAE) will
. The Full Flag (FF) will reset to HIGH. The Empty
n
, including the first
0
-Q
n
maintain
9
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
TM
to the outputs Q
after the first write. REN does not need to be asserted LOW. In order to access
all other words, a read must be executed using REN. The RCLK LOW to HIGH
transition after the last word has been read from the FIFO, Output Ready (OR)
will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read
operations. REN is ignored when the FIFO is empty.
OUTPUT ENABLE (OE)
receive data from the output register. When OE is disabled (HIGH), the Q output
data bus is in a high-impedance state.
LOAD (LD)
12-bit offset registers with data on the inputs, or read on the outputs. When the
Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is
written into the Empty Offset register on the first LOW-to-HIGH transition of the
Write Clock (WCLK). When the LD pin and WEN are held LOW then data is
written into the Full Offset register on the second LOW-to-HIGH transition of
WCLK. The third transition of WCLK again writes to the Empty Offset register.
or two offset registers can be written and then by bringing the LD pin HIGH, the
FIFO is returned to normal read/write operation. When the LD pin is set LOW,
and WEN is LOW, the next offset register in sequence is written.
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
LD
read is performed on the LOW-to-HIGH transition of RCLK.
0
0
1
1
17
17
In the FWFT mode, the first word written to an empty FIFO automatically goes
When Output Enable (OE) is enabled (LOW), the parallel output buffers
The IDT72V205/72V215/72V225/72V235/72V245 devices contain two
However, writing all offset registers does not have to occur at one time. One
Figure 3. Offset Register Location and Default Values
WEN
0
1
0
1
n
11
11
, on the third valid LOW to HIGH transition of RCLK + t
Figure 2. Writing to Offset Registers
WCLK
001FH (72V205) 003FH (72V215):
007FH (72V225/72V235/72V245)
001FH (72V205) 003FH (72V215):
007FH (72V225/72V235/72V245)
EMPTY OFFSET REGISTER
FULL OFFSET REGISTER
DEFAULT VALUE
DEFAULT VALUE
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Write Into FIFO
No Operation
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Selection
OCTOBER 22, 2008
4294 drw 04
SKEW
0
0