IDT72V205L15TF IDT, Integrated Device Technology Inc, IDT72V205L15TF Datasheet - Page 7

• Manufacturer Part Number: IDT72V205L15TF
• Description: IC FIFO SYNC 16KX9 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L15TF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72V205L15TF; 800-1510

Q
on the next LOW-to-HIGH transition of RCLK. The first transition of RCLK will
present the empty offset value to the data output lines. The next transition of RCLK
will present the full offset value. Offset register content can be read out in the IDT
Standard mode only. It cannot be read in the FWFT mode.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
during the "Configuration at Reset" cycle described in Table 3 with either
asynchronous or synchronous timing for PAE and PAF flags.
PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to
HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is asserted
LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the
LOW-to-HIGH transition of RCLK. For detail timing diagrams, see Figure 13 for
asynchronous PAE timing and Figure 14 for asynchronous PAF timing.
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
TABLE 2 — STATUS FLAGS FOR FWFT MODE
NOTES:
1. n = Empty Offset (Default Values : IDT72V205 n=31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127)
2. m = Full Offset (Default Values : IDT72V205 m=31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127)
NOTES:
1. n = Empty Offset (Default Values : IDT72V205 n = 31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127)
2. m = Full Offset (Default Values : IDT72V205 m = 31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127)
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
11
129 to (256-(m+1))
130 to (257-(m+1))
The contents of the offset registers can be read on the data output lines Q
The IDT72V205/72V215/72V225/72V235/72V245 can be configured
If asynchronous PAE/PAF configuration is selected (as per Table 3), the
when the LD pin is set LOW and REN is set LOW. Data can then be read
(256-m) to 255
(257-m) to 256
(n + 1) to 128
(n + 2) to 129
1 to (n + 1)
IDT72V205
IDT72V205
1 to n
256
257
0
0
(1)
(1)
(2)
(2)
257 to (512-(m+1))
258 to (513-(m+1))
(512-m) to 511
(513-m) to 512
(n + 1) to 256
(n + 2) to 257
1 to (n + 1)
IDT72V215
IDT72V215
1 to n
512
513
0
0
(1)
(1)
(2)
Number of Words in FIFO
(2)
513 to (1,024-(m+1))
514 to (1,025-(m+1))
(1,024-m) to 1,023
(1,025-m) to 1,024
Number of Words in FIFO
(n + 1) to 512
IDT72V225
(n + 2) to 513
1 to (n + 1)
IDT72V225
1 to n
1,024
1,025
0
0
(1)
(1)
(2)
(2)
1,025 to (2,048-(m+1))
0
1,026 to (2,049-(m+1))
-
(2,048-m) to 2,047
7
(2,049-m) to 2,048
(n + 1) to 1,024
(n + 2) to 1,025
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. For detail
timing diagrams, see Figure 22 for synchronous PAE timing and Figure 23 for
synchronous PAF timing.
REGISTER-BUFFERED FLAG OUTPUT SELECTION
during the "Configuration at Reset" cycle described in Table 4 with single, double
or triple register-buffered flag output signals. The various combinations avail-
able are described in Table 4 and Table 5. In general, going from single to
double or triple buffered flag outputs removes the possibility of metastable flag
indications on boundary states (i.e, empty or full conditions). The trade-off is the
addition of clock cycle delays for the respective flag to be asserted. Not all
combinations of register-buffered flag outputs are supported. Register-buffered
outputs apply to the Empty Flag and Full Flag only. Partial flags are not effected.
Table 4 and Table 5 summarize the options available.
TM
IDT72V235
1 to (n + 1)
IDT72V235
1 to n
2,048
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
The IDT72V205/72V215/72V225/72V235/72V245 can be configured
2,049
0
0
(1)
(1)
(2)
(2)
2,049 to (4,096-(m+1))
2,050 to (4,097-(m+1))
(4,096-m) to 4,095
(4,097-m) to 4,096
(n + 1) to 2,048
(n + 2) to 2,049
1 to (n + 1)
IDT72V245
IDT72V245
1 to n
4,096
4,097
0
0
(1)
(1)
COMMERCIAL AND INDUSTRIAL
(2)
(2)
TEMPERATURE RANGES
FF PAF
H
H
H
H
H
IR PAF HF PAE OR
L
H
L
L
L
L
L
OCTOBER 22, 2008
H
H
H
H
L
L
H
H
H
H
L
L
HF
H
H
H
H
H
H
L
L
L
L
L
L
PAE EF
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
H
L
L
L
L
L