IDT72V205L15TF IDT, Integrated Device Technology Inc, IDT72V205L15TF Datasheet - Page 24

• Manufacturer Part Number: IDT72V205L15TF
• Description: IC FIFO SYNC 16KX9 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L15TF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72V205L15TF; 800-1510

DEPTH EXPANSION CONFIGURATION (FWFT MODE)
one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to the
sum of the depths associated with each single FIFO. Figure 31 shows a depth
expansion using two IDT72V205/72V215/72V225/72V235/72V245 devices.
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next (“ripple down”) until it finally
appears at the outputs of the last FIFO in the chain–no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device’s OR line goes LOW,
enabling a write to the next FIFO in line.
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO’s
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
where N is the number of FIFOs in the expansion and T
Note that extra cycles should be added for the possibility that the t
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
HF
DATA IN
PAF
WRITE ENABLE
INPUT READY
WRITE CLOCK
In FWFT mode, the FIFOs can be connected in series (the data outputs of
Care should be taken to select FWFT mode during Master Reset for all FIFOs
For an empty expansion configuration, the amount of time it takes for OR of
n
(N – 1)*(4*transfer clock) + 3*T
Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration
Dn
WCLK
IR
WEN
(0,1)
FL
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
72V205
72V215
72V225
72V235
72V245
GND
RXI
WXI
TRANSFER CLOCK
V
RCLK
CC
RCLK
REN
RCLK
OR
OE
Qn
is the RCLK period.
SKEW1
GND
n
24
TM
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
configuration will “bubble up” from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO’s IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
The “ripple down” delay is only noticeable for the first word written to an empty
The first free location created by reading from a full depth expansion
For a full expansion configuration, the amount of time it takes for IR of the first
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
IR
Dn
WCLK
WEN
(N – 1)*(3*transfer clock) + 2 T
(0,1)
FL
72V205
72V215
72V225
72V235
72V245
GND
RXI
COMMERCIAL AND INDUSTRIAL
WXI
V
RCLK
CC
REN
OR
OE
Qn
TEMPERATURE RANGES
OUTPUT ENABLE
OCTOBER 22, 2008
WCLK
OUTPUT READY
n
READ ENABLE
READ CLOCK
WCLK
DATA OUT
4294 drw 31
is the WCLK
PAE
SKEW1
HF