IDT72V36100L15PFI IDT, Integrated Device Technology Inc, IDT72V36100L15PFI Datasheet - Page 33

IC FIFO SYNC II 36BIT 128-TQFP

IDT72V36100L15PFI

Manufacturer Part Number
IDT72V36100L15PFI
Description
IC FIFO SYNC II 36BIT 128-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V36100L15PFI

Function
Synchronous
Memory Size
2.3K (64 x 36)
Data Rate
166MHz
Access Time
15ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Configuration
Dual
Density
2.25Mb
Access Time (max)
10ns
Word Size
36b
Organization
64Kx36
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
40mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V36100L15PFI
800-1529

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V36100L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V36100L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW.
3. W
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
Q
WCLK
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
0
RCLK
WEN
1
REN
- Q
PAE
PAF
= first word written to the FIFO after Master Reset, W
HF
EF
RT
n
t
ENS
W
x
t
A
t
ENS
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
W
t
RTS
x+1
2
= second word written to the FIFO after Master Reset.
1
t
A
t
t
ENH
HF
t
SKEW2
1
TM
36-BIT FIFO
W
1 (3)
33
2
t
PAFS
2
t
A
W
2 (3)
3
t
t
PAES
A
COMMERCIAL AND INDUSTRIAL
W
TEMPERATURE RANGES
3 (3)
OCTOBER 22, 2008
6117 drw18
t
t
ENH
A
W
4

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