IDT72V36100L15PFI IDT, Integrated Device Technology Inc, IDT72V36100L15PFI Datasheet - Page 37
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IDT72V36100L15PFI
Manufacturer Part Number
IDT72V36100L15PFI
Description
IC FIFO SYNC II 36BIT 128-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V36110L7-5BB.pdf
(48 pages)
Specifications of IDT72V36100L15PFI
Function
Synchronous
Memory Size
2.3K (64 x 36)
Data Rate
166MHz
Access Time
15ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Configuration
Dual
Density
2.25Mb
Access Time (max)
10ns
Word Size
36b
Organization
64Kx36
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
40mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V36100L15PFI
800-1529
800-1529
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V36100L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V36100L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
2. In FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
WCLK
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
WCLK
RCLK
RCLK
WEN
WEN
REN
REN
PAE
HF
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
[
D-1
n + 1 words in FIFO
t
2
CLKH
D/2 words in FIFO
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
n words in FIFO
+ 1
]
words in FIFO
t
CLKH
(1)
(2) ,
,
(2)
(3)
t
t
ENS
ENS
TM
t
CLKL
36-BIT FIFO
t
CLKL
37
t
ENH
t
t
ENH
PAEA
t
HF
t
ENS
t
ENS
[
n + 1 words in FIFO
n + 2 words in FIFO
D/2 + 1 words in FIFO
D-1
2
+ 2
]
words in FIFO
t
PAEA
t
HF
(2) ,
(3)
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
[
n + 1 words in FIFO
D-1
TEMPERATURE RANGES
n words in FIFO
2
D/2 words in FIFO
OCTOBER 22, 2008
+ 1
]
words in FIFO
6117 drw27
6117 drw26
(2) ,
(1)
,
(3)
(2)