74HCT7403D,512 NXP Semiconductors, 74HCT7403D,512 Datasheet - Page 26

• Manufacturer Part Number: 74HCT7403D,512
• Description: IC FIFO REGISTER 64X4 3ST 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT7403D,512

• Function: Asynchronous, Synchronous
• Memory Size: 256 (64 x 4)
• Data Rate: 15MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Logic Family: HCT
• Logical Function: FIFO Register
• Number Of Elements: 1
• Number Of Bits: 4
• Number Of Inputs: 4
• Number Of Outputs: 4
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Output Type: 3-State
• Polarity: Non-Inverting
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 16
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Quiescent Current: 50uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74HCT7403D; 74HCT7403D; 933999390512

Philips Semiconductors
Notes to Fig.22
1. FIFO
2. Unload one word from FIFO
3. DIR
4. DOR
5. DOR
6. DIR
September 1993
handbook, full pagewidth
4-Bit x 64-word FIFO register; 3-state
data is shifted out of FIFO
bubble-up of empty location
B
A
A
A
A
and SO
goes HIGH; (bubble-up delay after SO
and SI
and SI
and FIFO
A
B
B
go HIGH; flag indicates valid data is again available at FIFO
pulse HIGH; (bubble-up delay after SO
go LOW; flag indicates the output stage of FIFO
B
initially full, SI
DOR B
Fig.22 FIFO to FIFO communication; output timing under full condition.
SO B
DIR B
DOR A SI B
DIR A
Q nA
D
SO A
nB
A
B
; SO pulse applied, results in DOR pulse
1
B
held HIGH in anticipation of shifting in new data as an empty location bubbles-up
V M
(1)
V M
(1)
A
LOW) an empty location is present at input stage of FIFO
2
bubble - up
delay
B
26
LOW) data is loaded into FIFO
V M
4
(1)
A
V M
3
is busy, shift-in to FIFO
(1)
bubble - up
A
delay
output stage, SI
5
V M
MGA667
B
(1)
6
as a result of the DIR pulse,
B
74HC/HCT7403
is complete
B
is held HIGH, awaiting
Product specification
A
.