74HCT7403D,512 NXP Semiconductors, 74HCT7403D,512 Datasheet - Page 28

• Manufacturer Part Number: 74HCT7403D,512
• Description: IC FIFO REGISTER 64X4 3ST 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT7403D,512

• Function: Asynchronous, Synchronous
• Memory Size: 256 (64 x 4)
• Data Rate: 15MHz
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Logic Family: HCT
• Logical Function: FIFO Register
• Number Of Elements: 1
• Number Of Bits: 4
• Number Of Inputs: 4
• Number Of Outputs: 4
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Output Type: 3-State
• Polarity: Non-Inverting
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 16
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Quiescent Current: 50uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Access Time: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 74HCT7403D; 74HCT7403D; 933999390512

Philips Semiconductors
Sequence 2 (FIFO
After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIR
being full (5). DOR
Sequence 3 (FIFO
When 65 words are shifted in, DOR
HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full
(7). Additional pulses have no effect.
Sequence 4 (both FIFOs full, starting SHIFT-OUT process)
SI
locations to bubble-up to the input stage of FIFO
input of FIFO
second empty location reaches the input stage of FIFO
Sequence 5 (FIFO
At the start of sequence 5 FIFO
in, in sequence 4. An additional series of SO
into FIFO
Sequence 6 (FIFO
After the next SO
DOR
available at the output Q
PACKAGE OUTLINES
See
September 1993
A
4-Bit x 64-word FIFO register; 3-state
is held HIGH and two SO
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
B
remains LOW due to both FIFOs being empty (14). Additional SO
B
. DOR
A
, a DIR
A
B
remains LOW (12).
pulse, DIR
A
B
A
A
B
goes LOW due to FIFO
runs full)
runs full)
runs empty)
runs empty)
A
pulse is generated (10) and a new word is shifted into FIFO
n
.
B
B
remains HIGH due to the input stage of FIFO
pulses are applied (8). These pulses shift out two words and thus allow two empty
A
contains 63 valid words due to two words being shifted out and one word being shifted
A
remains HIGH due to valid data remaining at the output of FIFO
A
B
being empty.
pulses are applied. After 63 SO
B
, and proceed to FIFO
A
, after which DIR
.
28
A
B
(9). When the first empty location arrives at the
A
pulses have no effect. The last word remains
remains HIGH (11).
B
being empty. After another 63 SO
B
pulses, all words from FIFO
A
. SI
A
is made LOW and now the
B
remains LOW due to FIFO
74HC/HCT7403
Product specification
A
. Q
nA
A
are shifted
remains
B
pulses,
B