LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 184

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

11.2.2
11.2.3
March 22, 2006
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid
start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are
also performed, and their status accompanies the data that is written to the receive FIFO.
Figure 11-2.
Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register
(see page 195) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
Divisor (UARTFBRD) register (see page 196). The baud-rate divisor has the following
relationship to the system clock:
BRD (Baud-Rate Divisor) = BRDI + BRDF = SysClk / (16 * Baud Rate)
Where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal
place.
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD
register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64,
and adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16
error detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 197), the
UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only
updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
divisor must be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
Data Transmission
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra
four bits per character for status information. For transmission, data is written into the transmit
FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters
UARTIBRD write, UARTFBRD write, and UARTLCRH write
UARTFBRD write, UARTIBRD write, and UARTLCRH write
UARTIBRD write and UARTLCRH write
UARTFBRD write and UARTLCRH write
). This reference clock is divided by 16 to generate the transmit clock, and is used for
UART Character Frame
UnTX
1
0
Start
n
Preliminary
LSB
5-8 data bits
MSB
if enabled
Parity bit
stop bits
1-2
LM3S101 Data Sheet
184