LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 76

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

March 22, 2006
Reset
Reset
Type
Type
Run-Mode, Sleep-Mode, and Deep-Sleep-Mode Clock Gating Control 1 (RCGC1, SCGC1, and DCGC1)
Offset 0x104, 0x114, and 0x124
RO
RO
31
15
0
0
Register 22: Run-Mode Clock Gating Control 1 (RCGC1), offset 0x104
Register 23: Sleep-Mode Clock Gating Control 1 (SCGC1), offset 0x114
Register 24: Deep-Sleep-Mode Clock Gating Control 1 (DCGC1), offset 0x124
These registers control the clock gating logic. Each bit controls a clock enable for a given
interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is
unclocked and disabled (saving power). The reset state of these bits is 0 (unclocked) unless
otherwise noted, so that all functional units are disabled. It is the responsibility of software to
enable the ports necessary for the application. Note that these registers may contain more bits
than there are interfaces, functions, or units to control. This is to assure reasonable code
compatibility with other family and future parts.
RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and
DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration
(RCC) register (see page 70) specifies that the system uses sleep modes.
The bit diagram for these three registers is shown below. Bits have the same definitions as DC2
(see page 57) and use DC2 as the mask.
RO
RO
30
14
0
0
RO
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
RO
RO
27
11
0
0
reserved
RO
RO
26
10
0
0
COMP1 COMP0
R/W
RO
25
0
9
0
Preliminary
R/W
RO
24
0
8
0
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
reserved
SSI
R/W
RO
20
0
4
0
RO
RO
19
0
3
0
reserved
LM3S101 Data Sheet
RO
RO
18
0
2
0
GPTM1 GPTM0
R/W
RO
17
0
1
0
UART0
R/W
R/W
16
0
0
0
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