LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 27

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

ARM Cortex-M3 Processor Core
2.1
2.2
2.2.1
27
Block Diagram
Figure 2-1.
Functional Description
Important:
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1. As noted in
the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible
in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC).
Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-
compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug
Port,” of the ARM® Cortex™-M3 Technical Reference Manual does not apply to the Stellaris
devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
Serial Wire JTAG
Debug Port
The ARM® Cortex™-M3 Technical Reference Manual describes all the features of
an ARM Cortex-M3 in detail. However, these features differ based on the
implementation. This section describes the Stellaris implementation.
CPU High-Level Block Diagram
Controller
Vectored
Interrupt
Nested
Private Peripheral
Access Port
Adv. High-
Interrupts
Perf. Bus
(internal)
Debug
Sleep
Bus
Preliminary
Breakpoint
Patch and
Instructions
Flash
CM3 Core
Data
Watchpoint
and Trace
Matrix
Bus
Data
Cortex-M3
ARM
Adv. Peripheral
Instrumentatio
Macrocell
n Trace
Bus
Interface
Trace
I-code bus
D-code bus
System bus
Port
Unit
March 22, 2006
Peripheral
(external)
(SWO)
Serial
Trace
Table
Private
ROM
Wire
Port
Bus