LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 98

no-image

LM3S101-CRN20-XNPT

Manufacturer Part Number
LM3S101-CRN20-XNPT
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
8.4
Table 8-3.
March 22, 2006
Offset
0x40C
0x41C
0x000
0x400
0x404
0x408
0x410
0x414
0x418
0x420
Name
GPIODATA
GPIODIR
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIOAFSEL
Table 8-2.
a. X=Ignored (don’t care bit)
Register Map
Table 8-2 lists the GPIO registers. All addresses given are relative to that GPIO port’s base
address:
The GPIO registers in this chapter are duplicated in each GPIO block, however depending on the
block, all eight bits may not be connected to a GPIO pad (see Figure 8-1 on page 94). In those
cases, writing to those unconnected bits has no effect and reading those unconnected bits returns
no meaningful data.
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
Register
GPIO Port A: 0x40004000
GPIO Port B: 0x40005000
GPIO Port C: 0x40006000
GPIO Register Map
Interrupt Configuration Example
Desired Interrupt
1=High level, or
0=Low level, or
Event Trigger
0=single edge
negative edge
1=not masked
1=both edges
positive edge
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0=masked
see note
0=edge
1=level
Reset
a
Type
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
Preliminary
X
X
X
7
0
Description
Data
Data direction
Interrupt sense
Interrupt both edges
Interrupt event
Interrupt mask enable
Raw interrupt status
Masked interrupt status
Interrupt clear
Alternate function select
X
X
X
6
0
5
X
X
X
0
Pin 2 Bit Value
X
X
X
4
0
3
X
X
X
0
a
2
0
0
1
1
LM3S101 Data Sheet
1
X
X
X
0
See
page
100
101
102
103
104
105
106
107
108
109
X
X
X
0
0
98

Related parts for LM3S101-CRN20-XNPT