LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 70

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

March 22, 2006
Reset
Reset
Type
Type
Bit/Field
31:28
Run-Mode Clock Configuration (RCC)
Offset 0x060
27
RO
RO
31
15
0
0
reserved
Register 17: Run-Mode Clock Configuration (RCC), offset 0x060
This register is defined to provide source control and frequency speed.
RO
RO
30
14
reserved
0
0
Reserved
Name
PWRDN
ACG
R/W
RO
29
13
0
1
OEN
R/W
RO
28
12
0
1
BYPASS
ACG
Type
R/W
R/W
R/W
27
11
RO
0
1
PLLVER
R/W
R/W
26
10
1
0
Reset
R/W
R/W
25
1
9
1
0
0
Preliminary
SYSDIV
R/W
R/W
24
1
8
0
XTAL
Description
Reserved bits return an indeterminate value, and should
never be changed.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode
Clock Gating Control (SCGCn) registers (see page 75)
and Deep-Sleep-Mode Clock Gating Control (DCGCn)
registers (see page 75) if the controller enters a Sleep or
Deep-Sleep mode (respectively). If set, the SCGCn or
DCGCn registers are used to control the clocks distributed
to the peripherals when the controller is in a sleep mode.
Otherwise, the Run-Mode Clock Gating Control (RCGCn)
registers (see page 75) are used when the controller enters
a sleep mode.
The RCGCn registers are always used to control the clocks
in Run mode.
This allows peripherals to consume less power when the
controller is in a sleep mode and the peripheral is unused.
R/W
R/W
23
1
7
1
USESYS
R/W
R/W
22
0
6
1
R/W
RO
21
0
5
0
OSCSRC
R/W
RO
20
0
4
0
BOSCVERMOSCVER
R/W
RO
19
0
3
0
reserved
LM3S101 Data Sheet
R/W
RO
18
0
2
0
RO
RO
17
0
1
0
reserved
RO
RO
16
0
0
0
70