LM3S101-CRN20-XNPT Luminary Micro, Inc., LM3S101-CRN20-XNPT Datasheet - Page 48

• Manufacturer Part Number: LM3S101-CRN20-XNPT
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Figure 6-2.
6.1.4.2
6.1.4.3
6.1.4.4
March 22, 2006
OSC1
OSC2
a. These are bit fields within the Run-Mode Clock Configuration (RCC) register
PLL Frequency Configuration
The user does not have direct control over the PLL frequency, but is required to match the external
crystal used to an internal PLL-Crystal table. This table is used to create the best fit for PLL
parameters to the crystal chosen. Not all crystals result in the PLL operating at exactly 200 MHz,
though the frequency will be within
result of the lookup is kept in the XTAL to PLL Translation (PLLCTL) register (see page 74).
Table 6-3 on page 72 describes the available crystal choices and default programming of the
PLLCTL register. The crystal number is written into the XTAL field of the Run-Mode Clock
Configuration (RCC) register (see page 70). Any time the XTAL field changes, a read of the
internal table is performed to get the correct value. Table 6-3 on page 72 describes the available
crystal choices and default programming values.
PLL Modes
The PLL has two modes of operation: Normal and Power-Down
The modes are programmed using the Run-Mode Clock Configuration (RCC) register fields as
shown in Table 6-4 on page 73.
PLL Operation
If the PLL configuration is changed, the PLL output is not stable for a period of time (PLL
T
The PLL is changed by one of the following:
A counter is defined to measure the T
oscillator. The range of the boot oscillator has been taken into account and the down counter is set
to 0x3000 (that is, ~800 us at a 15-MHz boot oscillator clock). Hardware is provided to keep the
PLL from being used as a system clock until the T
1-8 MHz
15 MHz
READY
Main
Boot
Osc
Osc
Main Clock Tree
Normal: The PLL multiplies the input clock reference and drives the output.
Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the
output.
Change to the XTAL value in the Run-Mode Clock Configuration (RCC) register (see
page 70)—writes of the same value will not cause a relock).
Change in the PLL from Power-Down to Normal mode.
=0.5 ms) and during this time, the PLL is not usable as a clock reference.
÷4
OSCSRC
a
±
Preliminary
PWRDN
(200MHz
1%; non-exact values are fine, if tolerated by the system. The
XTAL
OEN
output )
PLL
READY
a
a
a
requirement. The counter is clocked by the boot
BYPASS
READY
a
condition is met after one of the two
SYSDIV
a
USESYS
LM3S101 Data Sheet
a
System Clock
48