EM636327Q-7 Etron Technology Inc., EM636327Q-7 Datasheet
EM636327Q-7
Related parts for EM636327Q-7
EM636327Q-7 Summary of contents
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... EM636327R-10 100MHz EM636327TQ-10 100MHz EM636327JT-10 100MHz EM636327Q-8 125MHz EM636327R-8 125MHz EM636327TQ-8 125MHz EM636327JT-8 125MHz EM636327Q-7 143MHz EM636327TQ-7 143MHz EM636327Q-6 166MHz EM636327TQ-6 166MHz EM636327Q-55 183MHz EM636327TQ-55 183MHz page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
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Block Diagram CLK CLOCK BUFFER CKE CS# RAS# COMMAND CAS# DECODER WE# GENERATOR DSF COLUMN COUNTER A9 ADDRESS A0 BUFFER A8 BS REFRESH COUNTER Forward Type DQ3 DDQ DQ4 3 DQ5 SSQ DQ6 6 ...
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Pin Descriptions Table 1 shows the details for pin number, symbol, type, and description. Pin Number Symbol Type Description 55 CLK Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on the positive edge ...
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DSF Input Define Special Function: The DSF signal defines the operation commands in conjunction with the RAS# and CAS# and WE# signals and is latched at the positive edges of CLK. The DSF input is used to select the ...
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Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Command BankActivate & Masked Write Disable BankActivate & Masked Write Enable BankPrecharge PrechargeAll ...
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Commands 1 BankActivate & Masked Write Disable command (RAS# = "L", CAS# = "H", WE# = "H", DSF = "L" Bank, A0-A9 = Row Address) The BankActivate command activates the idle bank designated by the BS (Bank Select) ...
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The burst length, burst sequence, and CAS# latency are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the ...
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CLK DQM COM MAND NOP READ A DQ's : "H" or "L" Read to Write Interval CLK DQM COM MAND NOP NOP CAS# latency=1 t CK1 , DQ's CAS# latency=2 t CK2 , DQ's ...
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CLK Bank, ADDRESS Col A COM M AND READ A NOP CAS# latency=1 DOUT CK1 , DQ's CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's Read to Precharge 6 Read ...
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DSF BankActivate command MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 Note: Only the lower byte is shown. The operation is identical for other bytes. Write Per Bit (I/O Mask) Block Diagram A write burst without the ...
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Once the Read command is registered, the data inputs will be ignored and writes will not be executed CLK COM MAND NOP WRITE A CAS# ...
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Block Write command is used to mask specific column/byte combinations within the block. The mapping of the DQ inputs to the column/byte combinations is shown in following table. The overall Block Write mask consists of a ...
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DQ Column Address DQ Planes Inputs A2 A1 DQ0 0 0 DQ1 0 0 DQ2 0 1 DQ3 0 1 DQ4 1 0 DQ5 1 0 DQ6 1 1 DQ7 1 1 DQ8 0 0 DQ9 0 0 DQ10 0 ...
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Block Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", DSF = "H" Bank "H", A3-A7 = Column Address, DQ0-DQ31 = Column Mask) The Block Write and AutoPrecharge command performs the ...
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The mode register is divided into various fields depending on functionality. Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length ...
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This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following ...
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Burst Stop command (RAS# = "H", CAS# = "H", WE# = "L", DSF = "L") The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the ...
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SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms) (RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "L", BS, A0-A9 = Don't care) The SelfRefresh is another refresh mode available in the ...
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Absolute Maximum Rating Symbol Input, Output Voltage IN OUT Power Supply Voltage DD DDQ T Operating Temperature OPR T Storage Temperature STG T Soldering Temperature (10s) SOLDER P Power Dissipation D I Short Circuit ...
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Recommended D.C. Operating Conditions (V Description/Test condition Operating Current t t (min), Outputs Open Address changed once during CK Burst Length = 2 Precharge Standby Current in non-power down mode (min), CS ...
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Electrical Characteristics and Recommended A.C. Operating Conditions (V = 3.3V¡Ó0.3V 0~70 C) (Note Symbol A.C. Parameter t Row cycle time RC (same bank) t RAS# to CAS# delay RCD (same bank) t Precharge ...
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Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced These parameters depend on the cycle rate and these values are measured by the ...
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Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to V and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time. 2) ...
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Timing Waveforms Figure 1. AC Parameters for Write Timing CLK CK2 CKE CS# RAS WE# DSF ...
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Figure 2. AC Parameters for Read Timing CLK CK2 CH CKE RAS WE# DSF RAx ...
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Figure 3. Auto Refresh (CBR CLK t CK2 CKE CS# RAS WE# DSF DQM DQ PrechargeAll AutoRefresh Command Command Preliminary (Burst Length=4, ...
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Figure 4. Power on Sequene and Auto Refresh (CBR CLK t CK2 High level CKE is reauired CS# RAS# CAS# WE# DSF Address Key DQM t ...
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Figure 5. Self Refresh Entry & Exit Cycle Clock *Note 2 *Note 1 CKE t IS CS# RAS# *Note WE# DSF DQM Hi-Z DQ Self Refresh Enter ...
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Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RAx RAx CAx DQM ...
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Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAx CAx RAx DQM ...
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Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAx RAx CAx ...
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Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = CLK t CK1 CKE CS# RAS WE# DSF RAx ...
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Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAx RAx CAx DQM ...
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Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAx RAx CAx DQM ...
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Figure 8. Power Down Mode and Clock Mask CLK t CK2 t IS CKE CS WE# BS RAx A 9 RAx A0~ A8 DQM Hi-Z DQ ACTIVE STANDBY Activate ...
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Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RAw RAw CAw DQM Hi-Z ...
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Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RAw CAw RAw DQM Hi-Z ...
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Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RAw RAw CAw DQM Hi-Z ...
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Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS WE# DSF RBw RBw CBw DQM Hi-Z ...
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Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS WE# DSF RBw RBw CBw DQM Hi-Z ...
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Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS WE# DSF RBw CBw RBw DQM Hi-Z ...
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Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 CKE High CS# RAS WE# DSF BS RBx A 9 RBx CBx RCD t ...
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Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF RBx RBx CBx RCD ...
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Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RBx RBx CBx RCD ...
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Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 High CKE CS# RAS WE# DSF RAx RAx CAx t RCD DQM ...
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Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF RAx RAx CAx t RCD DQM ...
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Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF RAx RAx CAx RCD DQM ...
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Figure 13.1. Read and Write Cycle CLK t CK1 CKE CS# RAS WE# DSF RAx RAx CAx DQM Hi-Z DQ Ax0 Ax1 Ax2 Activate Command Bank ...
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Figure 13.2. Read and Write Cycle CLK t CK2 CKE CS# RAS WE# DSF RAx RAx CAx DQM Hi-Z DQ Ax0 Activate Read Command Command Bank ...
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Figure 13.3. Read and Write Cycle CLK t CK3 CKE CS# RAS WE# DSF RAx CAx RAx DQM Hi-Z DQ Read Activate Command Command Bank A ...
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Figure 14.1. Interleaving Column Read Cycle CLK t CK1 CKE CS WE# DSF RAx RBw RAx RBw RAx A0 RCD AC1 DQM Hi-Z ...
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Figure 14.2. Interleaving Column Read Cycle CLK t CK2 CKE CS# RAS WE# DSF RAx RAx CAy RAx RAx RCD AC2 DQM Hi-Z DQ ...
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Figure 14.3. Interleaved Column Read Cycle CLK t CK3 CKE CS# RAS WE# DSF BS RAx RBx A 9 RAx CAx RBx RCD DQM Hi-Z DQ Activate Read ...
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Figure 15.1. Interleaved Column Write Cycle CLK t CK1 CKE CS WE# DSF RAx RBw RAx CAx RBw A0 RCD DQM t RRD Hi-Z ...
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Figure 15.2. Interleaved Column Write Cycle CLK t CK2 CKE WE# DSF RAx RBw RAx CAx RBw A0~A8 t RCD DQM t RRD Hi-Z DQ ...
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Figure 15.3. Interleaved Column Write Cycle CLK t CK3 CKE CS# RAS WE# DSF RAx RBw RAx CAx RBw RCD DQM t > t RRD ...
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Figure 16.1. Auto Precharge after Read Burst CLK t CK1 High CKE CS# RAS WE# DSF BS RAx RBx A 9 RBx CBx RAx CAx DQM Hi-Z DQ Ax1 ...
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Figure 16.2. Auto Precharge after Read Burst CLK t CK2 High CKE CS DSF RAx RBx A 9 RAx RBx CAx DQM ...
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Figure 16.3. Auto Precharge after Read Burst CLK t CK3 High CKE CS# RAS WE# DSF BS RAx RBx A 9 CAx RAx RBx DQM Hi-Z DQ Activate Activate ...
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Figure 17.1. Auto Precharge after Write Burst CLK t CK1 High CKE CS# RAS WE# WE# BS RAx RBx A 9 RAx CAx RBx CBx DQM Hi-Z DQ DAx0 ...
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Figure 17.2. Auto Precharge after Write Burst CLK t CK2 High CKE CS# RAS WE# WE# BS RBx RAx A 9 RAx CAx RBx DQM Hi-Z DQ DAx0 DAx1 ...
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Figure 17.3. Auto Precharge after Write Burst CLK t CK3 High CKE CS WE# DSF BS RAx RBx A 9 CAx RAx RBx A0~ A8 DQM Hi-Z DQ DAx0 ...
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Figure 18.1. Full Page Read Cycle CLK t CK1 High CKE CS# RAS WE# DSF BS RAx RBx A 9 RAx CAx RBx RRD DQM Hi-Z DQ Ax+1 ...
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Figure 18.2. Full Page Read Cycle CLK t CK2 High CKE CS WE# DSF BS RAx RBx A 9 A0~ A8 RAx CAx RBx DQM Hi-Z DQ Ax+1 Ax+2 ...
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Figure 18.3. Full Page Read Cycle CLK t CK3 High CKE CS# RAS WE# DSF BS RAx RBx A 9 RAx CAx RBx DQM Hi-Z DQ Activate Read Activate ...
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Figure 19.1. Full Page Write Cycle CLK t CK1 High CKE CS# RAS WE# DSF BS RAx RBx A 9 CAx RBx RAx DQM Hi-Z DQ DAx DAx+ 1 ...
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Figure 19.2. Full Page Write Cycle CLK t CK2 High CKE CS# RAS WE# DSF BS RAx RBx RAx CAx RBx DQM Hi-Z DQ DAx DAx+ 1 ...
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Figure 19.3. Full Page Write Cycle CLK t CK3 High CKE CS# RAS WE# DSF BS RAx RBx A 9 RAx CAx RBx DQM Hi-Z DQ DAx DAx+ 1 ...
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Figure 20. Byte Write Operation CLK t CK2 High CKE CS# RAS DSF BS RAx CAx RAx DQM0 DQM1~3 DQ0 - DQ7 Ax0 DQ8 ...
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Figure 21. Burst Read and Single Write Operation CLK t CK2 High CKE CS# RAS WE# DSF BS RAx A 9 A0~ A8 RAx CAx DQM0 DQM1~3 Hi-Z DQ0 - DQ7 Ax0 Hi-Z ...
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Figure 22. Full Page Burst Read and Single Write Operation (Burst Length=Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF BS RAv A 9 RAv CAv A0~ A8 DQM0 ...
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Figure 23. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency= CLK t CK1 High CKE Begin Auto Begin Auto Precharge Precharge Bank B Bank A CS WE# DSF BS ...
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Figure 24. Full Page Random Column Read CLK t CK2 CKE CS DSF BS RAx RBx A 9 RAx RBx CAx CBx DQM ...
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Figure 25. Full Page Random Column Write CLK t CK2 CKE CS# RAS WE# DSF BS RAx RBx A 9 RAx RBx CAx CBx DQM t t RRD RCD ...
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Figure 26.1. Precharge Termination of a Burst CLK t CK1 CKE CS# RAS WE# DSF BS RAx A 9 RAx CAx DQM DQ DAx0 DAx1 DAx2 DAx3 DAx4 Activate ...
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Figure 26.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency= CLK t CK2 High CKE CS# RAS WE# DSF BS RAx A 9 RAx CAx ...
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Figure 26.3. Precharge Termination of a Burst (Burst Length= Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS WE# DSF BS RAx A 9 RAx CAx A0 ~ ...
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... Pin 14x20 mm Package Outline Drawing Information PIN #1 L (L1) SECTION EM636327Q-XX Symbol Definition min A Overall Height A1 Stand Off 0.25 A2 Body Thickness 2.60 b Lead Width 0.22 C Lead Thickness 0.13 D Terminal Dimension 22.95 D1 Package Body 19.90 D3 Reference E Terminal Dimension 16.95 E1 Package Body 13.90 E3 Reference e Lead Pitch L Foot Length 0.65 L1 Lead Length ...