EM636327Q-7 Etron Technology Inc., EM636327Q-7 Datasheet - Page 10

• Manufacturer Part Number: EM636327Q-7
• Description: 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
• Manufacturer: Etron Technology Inc.

Preliminary
Note: Only the lower byte is shown. The operation is identical for other bytes.
BankActivate
command
CLK
COMMAND
DQ's
DSF
Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst
length. An interrupt coming from Write/Block Write command can occur on any clock cycle
following the previous Write command (refer to the following figure).
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
A write burst without the auto precharge function may be interrupted by a subsequent
The Read command that interrupts a write burst without auto precharge function should be
Write Interrupted by a Write
T0
NOP
D
CK
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
Q
WRITE A
DIN A 0
T 1
1 Clk Interval
Write Per Bit (I/O Mask) Block Diagram
WRITE B
DIN B 0
T2
DQM0
DIN B 1
T3
NOP
(Burst Length = 4, CAS# Latency = 1, 2, 3)
10
DIN B 2
T4
NOP
DIN B 3
T5
NOP
0 = Masked
1 = Not Masked
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
T6
NOP
EM636327
T7
NOP
December
NOP
T8
DRAM
CELL
1998