EM636327Q-7 Etron Technology Inc., EM636327Q-7 Datasheet - Page 15

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EM636327Q-7

Manufacturer Part Number
EM636327Q-7
Description
512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
Manufacturer
Etron Technology Inc.
Datasheet
Preliminary
Column Address
Burst Length
The mode register is divided into various fields depending on functionality.
Data n
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only
supports burst length of 4 and 8.
--- Addressing Sequence of Sequential Mode
--- Addressing Sequence of Interleave Mode
CAS# Latency Field (A6~A4)
Data n
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n + m), in
the table is larger than 255, only the least significant 8 bits are effective.
A column access is started in the input column address and is performed by inverting
the address bits in the sequence shown in the following table.
A2
A3
0
0
0
0
1
1
1
1
0
1
Full Page: Column address is repeated until terminated.
0
n
A7
A7
A7
A7
A7
A7
A7
A7
2 words:
4 words:
8 words:
Addressing Mode
n+1
1
A1
A6
A6
A6
A6
A6
A6
A6
A6
0
0
1
1
0
0
1
1
Sequential
Interleave
n+2
2
A5
A5
A5
A5
A5
A5
A5
A5
Column Address
n+3
3
A4
A4
A4
A4
A4
A4
A4
A4
A0
0
1
0
1
0
1
0
1
15
n+4
A3
A3
A3
A3
A3
A3
A3
A3
4
Burst Length
Reserved
Reserved
Reserved
Full Page
n+5
A2
A2
A2
A2
A2# A1
A2# A1
A2# A1# A0
A2# A1# A0#
5
1
2
4
8
n+6
A1
A1
A1# A0
A1# A0#
6
A0
A0#
A0
A0#
n+7
7
-
-
4 words
Burst Length
n+255
255
EM636327
8 words
256
n
December
257
n+1
1998
-
-

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