EM636327Q-7 Etron Technology Inc., EM636327Q-7 Datasheet - Page 11

• Manufacturer Part Number: EM636327Q-7
• Description: 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
• Manufacturer: Etron Technology Inc.

Preliminary
8
CLK
COM MAND
CAS# latency=1
t CK1 , DQ's
CAS# latency=2
t CK2 , DQ's
CAS# latency=3
t CK3 , DQ's
CLK
DQM
COM MAND
ADDRESS
DQ
: don't care
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals t
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
the read burst length (refer to Figures 21 and 22 in Timing Waveforms).
Block Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "H", BS = Bank, A9 = "L", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
single data value, which was previously loaded in the Color register, is written to the block of eight
consecutive column locations addressed by inputs A3~A7. The information on the DQs which are
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
When the Burst-Read-Single-Write mode is selected, the write burst length is 1 regardless of
The block writes are non-burst accesses that write to eight column locations simultaneously. A
Write Interrupted by a Read
T0
NOP
BA N K
COL n
WRITE
DIN
T0
n
Input data for the write is masked.
WRITE A
T 1
DIN A 0
DIN A 0
DIN A 0
NOP
DIN
n + 1
T 1
t WR
READ B
don't care
don't care
T2
WR
BANK (S)
Precharge
/t
T2
CK
Write to Precharge
rounded up to the next whole number. In addition, the DQM
don't care
T3
NOP
DOUT B 0
(Burst Length = 4, CAS# Latency = 1, 2, 3)
11
NOP
T3
T4
NOP
DOUT B 1
DOUT B 0
t RP
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
NOP
T4
T5
NOP
DOUT B 2
DOUT B 0
DOUT B 1
Activate
ROW
T5
T6
NOP
DOUT B 3
DOUT B 2
DOUT B 1
EM636327
NOP
T6
DOUT B 3
T7
NOP
DOUT B 2
December
NOP
DOUT B 3
T8
1998