EM636327Q-7 Etron Technology Inc., EM636327Q-7 Datasheet - Page 18

• Manufacturer Part Number: EM636327Q-7
• Description: 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
• Manufacturer: Etron Technology Inc.

Preliminary
17 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
18 SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
19 Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in
20 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
21 Data Write / Output Enable, Data Mask / Output Disable command
(RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "L", BS, A0-A9 = Don't care)
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SGRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SGRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited
by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
NOP or Device Deselect commands must be issued for t
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 2048 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
Timing Waveforms)
(CKE = "L")
the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (32ms) since the command does not perform any
refresh operations.
Waveforms)
(CKE= "H")
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. t
subsequent commands can be issued after one clock cycle from the end of this command.
(DQM = "L", "H")
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
also used for device selection, byte selection and bus control in a memory system. DQM0 controls
DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and DQM3 controls
DQ24 to DQ31. DQM masks the DQ's by a byte regardless that the corresponding DQ's are in a
state of write-per-bit masking or pixel masking. Each DQM0-3 corresponds to DQ0-7, DQ8-15,
DQ16-23, and DQ24-31.
The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh
This command is used to exit from the SelfRefresh mode. Once this command is registered,
When the SGRAM is operating the burst cycle, the internal CLK is suspended(masked) from
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
During a write cycle, the DQM signal functions as a Data Mask and can control every word of
PDE
(min.) is required when the device exits from the PowerDown mode. Any
18
RC
(min.) because time is required for the
EM636327
December
1998