FAN73832 Fairchild Semiconductor, FAN73832 Datasheet - Page 13

• Manufacturer Part Number: FAN73832
• Description: Fan73832 Half-bridge Gate-drive Ic
• Manufacturer: Fairchild Semiconductor

FAN73832 Rev. 1.0.2
© 2006 Fairchild Semiconductor Corporation
Typical Application Information
1. Normal Operating Consideration
The FAN73832 is a single PWM input, half-bridge, gate-
drive IC with programmable dead-time and shutdown
functions.
The dead-time is set with a resistor (R
pin. The wide dead-time programming range provides
the flexibility to optimize drive signal timing for a
selection of switching devices (MOSFET or IGBT) and
applications.
The
accommodates resistor values from 20kΩ to 200kΩ with
a dead-time proportional to the R
If the DT/SD pin voltage decreases below 1.2V in the
normal operation, the IC enters shutdown mode.
The external dead-time setting resistor (R
above 20KΩ for normal operation in typical applications.
2. Under-Voltage Lockout (UVLO)
The FAN73832 has an under-voltage lockout (UVLO)
protection circuit for high- and low-side channels to
prevent malfunction when V
the specified threshold voltage. The UVLO circuitry
monitors the supply voltage (V
capacitor voltage (V
turn-on
time
BS
) antepenult.
delay
DD
and V
DT
circuitry
DD
resistance.
BS
) and bootstrap
DT
) at the DT/SD
are lower than
DT
(Dead-Time)
) is at least
13
3. Layout Consideration
For optimum performance of the high- and low-side gate
drivers, considerations must be taken during printed
circuit board (PCB) layout.
3.1 Supply Capacitors
If the output stages are able to quickly turn-on a
switching device with a high value of current, the supply
capacitors must be placed as close as possible to the
device pins (V
and V
inductance and resistance.
3.2 Gate Drive Loop
Current loops behave like an antenna, able to receive
and transmit noise. To reduce the noise coupling/emis-
sion and improve the power switch turn-on and off per-
formances, gate drive loops must be reduced as much
as possible.
3.3 Ground Plane
Ground plane must not be placed under or nearby the
high-voltage floating side to minimize noise coupling.
S
for the floating supply) to minimize parasitic
DD
and GND for the ground-tied supply, V
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B