IDT72V3652L10PF IDT, Integrated Device Technology Inc, IDT72V3652L10PF Datasheet - Page 12

• Manufacturer Part Number: IDT72V3652L10PF
• Description: IC BI FIFO 4096X36 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3652L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 147K (4K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3652L10PF

SYNCHRONIZED FIFO FLAGS
stages. This is done to improve flag signal reliability by reducing the probability
of metastable events when CLKA and CLKB operate asynchronously to one
another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/
ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show
the relationship of each port flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
selected. When the Empty Flag is HIGH, data is available in the FIFO’s RAM
for reading to the output register. When the Empty Flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
TABLE 4 — FIFO1 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
TABLE 5 — FIFO2 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
read operation necessary), it is not included in the FIFO memory count.
port A.
read operation necessary), it is not included in the FIFO memory count.
port A.
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is
Each FIFO is synchronized to its port clock through at least two flip-flop
(X2+1) to [2,048-(Y2+1)]
(X1+1) to [2,048-(Y1+1)]
(2,048-Y1) to 2,047
(2,048-Y2) to 2,047
IDT72V3652
IDT72V3652
1 to X1
1 to X2
2,048
2,048
0
0
(3)
(3)
Number of Words in FIFO
Number of Words in FIFO
(X1+1) to [4,096-(Y1+1)]
(X2+1) to [4,096-(Y2+1)]
(4,096-Y2) to 4,095
(4,096-Y1) to 4,095
IDT72V3662
IDT72V3662
1 to X1
1 to X2
4,096
4,096
0
0
(3)
(3)
(1,2)
(1,2)
TM
(X1+1) to [8,192-(Y1+1)]
(X2+1) to [8,192-(Y2+1)]
(8,192-Y1) to 8,191
(8,192-Y2) to 8,191
IDT72V3672
IDT72V3672
1 to X1
1 to X2
8,192
8,192
12
0
0
that reads data from its array. For both the FWFT and IDT Standard modes,
the FIFO read pointer is incremented each time a new word is clocked to its
output register. The state machine that controls an Output Ready flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2.
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port Clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
Flag will indicate the presence of data available for reading in a minimum of two
cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
(3)
(3)
EFB/ORB
EFA/ORA
H
H
H
H
H
H
H
H
L
L
Synchronized
Synchronized
to CLKB
to CLKA
COMMERCIAL TEMPERATURE RANGE
AEB
AEA
H
H
H
H
H
H
L
L
L
L
AFA
AFB
H
H
H
H
H
H
L
L
Synchronized
L
L
Synchronized
FEBRUARY 4, 2009
to CLKA
to CLKB
FFA/IRA
FFB/IRB
H
H
H
H
H
H
H
H
L
L