IDT72V3652L10PF IDT, Integrated Device Technology Inc, IDT72V3652L10PF Datasheet - Page 3

• Manufacturer Part Number: IDT72V3652L10PF
• Description: IC BI FIFO 4096X36 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3652L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 147K (4K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3652L10PF

memory is full or not. The IR and OR functions are selected in the First Word
Fall Through mode. IR indicates whether or not the FIFO has available memory
locations. OR shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
a programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate
when a selected number of words remain in the FIFO memory. AFA and AFB
indicate when the FIFO contains more than a selected number of words.
port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB
are two-stage synchronized to the port clock that reads data from its array.
Programmable offsets for AEA, AEB, AFA and AFB are loaded by using
Port A. Three default offset settings are also provided. The AEA and AEB
NOTE:
1. Pin 1 identifier in corner.
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
PIN CONFIGURATION (CONTINUED)
Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the
FWFT
GND
GND
V
V
V
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
CC
CC
CC
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TQFP (PN120-1, order code: PF)
TM
TOP VIEW
3
threshold can be set at 8, 16 or 64 locations from the empty boundary and the
AFA and AFB threshold can be set at 8, 16 or 64 locations from the full boundary.
All these choices are made using the FS0 and FS1 inputs during Reset.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
inputs) will immediately take the device out of the power down state.
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
The IDT72V3652/72V3662/72V3672 are characterized for operation from
Two or more devices may be used in parallel to create wider data paths.
CC
) is at a minimum. Initiating any operation (by activating control
COMMERCIAL TEMPERATURE RANGE
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
4660 drw03
B
B
B
B
GND
B
B
B
B
B
B
V
B
B
GND
B
B
B
B
B
B
GND
B
B
V
B
B
B
B
GND
FEBRUARY 4, 2009
35
34
33
32
31
30
29
28
27
26
CC
25
24
23
22
21
20
19
18
17
16
CC
15
14
13
12