IDT72V3652L10PF IDT, Integrated Device Technology Inc, IDT72V3652L10PF Datasheet - Page 14

• Manufacturer Part Number: IDT72V3652L10PF
• Description: IC BI FIFO 4096X36 10NS 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3652L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 147K (4K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3652L10PF

NOTES:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
2. If FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW.
NOTES:
1. t
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
EFB/ORB
FS1,FS0
A0 - A35
FFB/IRB
FFA/IRA
FS1,FS0
FFA/IRA
edge of CLKB is less than t
SKEW1
CLKA
CLKB
FWFT
RST1,
RST2
CLKB
CLKA
MBF1
RST1
ENA
AEB
AFA
is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight
4
0,0
t
RSTS
t
SKEW1
FSS
t
FSH
, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
t
t
t
PRF
PRF
PRF
1
2
t
PIR
t
PIR
AFA Offset
t
DS
(Y1)
TM
t
DH
t
ENS2
14
AEB Offset
t
POR
(X1)
t
FSS
t
ENH
AFB Offset
(Y2)
0,1
t
(1)
RSTH
(IDT Standard and FWFT Modes)
t
FSH
AEA Offset
COMMERCIAL TEMPERATURE RANGE
(X2)
t
FWS
1
t
SKEW1
First Word to FIFO1
t
(1)
PIR
FEBRUARY 4, 2009
2
t
PIR
4660 drw05
4660 drw04