IDT72V3673L10PF IDT, Integrated Device Technology Inc, IDT72V3673L10PF Datasheet - Page 12

• Manufacturer Part Number: IDT72V3673L10PF
• Description: IC SYNCFIFO 8192X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3673L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 288K (8K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3673L10PF

TABLE 2 — — — — — PORT-A ENABLE FUNCTION TABLE
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
LOW, and EF/OR is HIGH (see Table 3). FIFO reads on Port B are
independent of any concurrent writes on Port A.
Selects and Write/Read selects are only for enabling write and read operations
and are not related to high-impedance control of the data outputs. If a port enable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
LOW, the next word written is automatically sent to the FIFO’s output register
by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag
HIGH. When the Output Ready flag is HIGH, data residing in the FIFO’s memory
array is clocked to the output register only when a read is selected using the
port’s Chip Select, Write/Read select, Enable, and Mailbox select.
TABLE 4 — FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
3. X is the Almost-Empty offset used by AE. Y is the Almost-Full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
read operation necessary), it is not included in the memory count.
CSA
CSB
The setup and hold time constraints to the port clocks for the port Chip
When operating the FIFO in FWFT mode and the Output Ready flag is
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
(X+1) to [2,048-(Y+1)]
(2,048-Y) to 2,047
IDT72V3653
1 to X
2,048
0
W/RA
W/RB
X
H
H
H
L
L
L
L
H
H
H
H
X
L
L
L
(3)
Number of Words in FIFO
ENA
ENB
X
H
H
H
H
X
H
H
H
H
L
L
L
L
L
L
(X+1) to [4,096-(Y+1)]
(4,096-Y) to 4,095
IDT72V3663
1 to X
4,096
MBA
0
MBB
X
X
H
H
H
L
L
L
H
H
H
X
X
L
L
L
(3)
(1,2)
TM
WITH
CLKB
CLKA
X
X
↑
↑
X
↑
X
↑
X
X
↑
↑
X
↑
X
↑
(X+1) to [8,192-(Y+1)]
(8,192-Y) to 8,191
IDT72V3673
12
1 to X
8,192
0
the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is
clocked to the output register only when a read is selected using the port’s
Chip Select, Write/Read select, Enable, and Mailbox select. Port A Write
timing diagram can be found in Figure 7. Relevant Port B Read timing
diagrams together with Bus-Matching and Endian select can be found in
Figure 8, 9 and 10.
SYNCHRONIZED FIFO FLAGS
stages. This is done to improve flag-signal reliability by reducing the probability
of metastable events when CLKA and CLKB operate asynchronously to one
another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
Data A (A0-A35) I/O
Data B (B0-B35) I/O
High-Impedance
High-Impedance
(3)
When operating the FIFO in IDT Standard mode, regardless of whether
Each FIFO is synchronized to its port clock through at least two flip-flop
Output
Output
Output
Output
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
EF/OR
H
H
H
H
Synchronized
L
to CLKB
COMMERCIAL TEMPERATURE RANGE
AE
H
H
H
L
L
Mail2 Read (Set MBF2 HIGH)
Mail1 Read (Set MBF1 HIGH)
Port Functions
Port Functions
FIFO Write
Mail1 Write
Mail2 Write
FIFO read
None
None
None
None
None
AF
None
None
None
None
None
H
H
H
Synchronized
L
L
to CLKA
FF/IR
H
H
H
H
L