IDT72V3673L10PF IDT, Integrated Device Technology Inc, IDT72V3673L10PF Datasheet - Page 5

• Manufacturer Part Number: IDT72V3673L10PF
• Description: IC SYNCFIFO 8192X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3673L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 288K (8K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3673L10PF

PIN DESCRIPTIONS (CONTINUED)
NOTE:
1. FS2, BM and Size inputs are not TTL compatible. These inputs should be tied to GND or V
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
MBA
MBB
MBF1
MBF2
RS1, RS2
PRS/
RT
RTM
SIZE
W/RA
W/RB
Symbol
(1)
Name
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register Flag
Mail2 Register Flag
Resets
Partial Reset/
Retransmit
Retransmit Mode
Bus Size Select
(Port B)
Port A Write/
Read Select
Port B Write/
Read Select
I/O
O
O
I
I
I
I
I
I
I
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and
a LOW level selects FIFO data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH
following either a Reset (RS1) or Partial Reset (PRS).
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH
following either a Reset (RS2) or Partial Reset (PRS).
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
sets the Port B output register to all zeroes. A LOW-to-HIGH transition on RS1 selects the programming
method (serial or parallel) and one of five programmable flag default offsets. It also configures Port
B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RS1 is LOW.
pin. If RTM is LOW, then a LOW on this pin initializes the FIFO read and write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently
selected bus size, endian arrangement, programming method (serial or parallel), and programmable
flag settings are all retained. If RTM is HIGH, then a LOW on this pin performs a Retransmit and initializes
the read pointer only, to the first memory location.
This pin is used in conjunction with the RT pin. When RTM is HIGH a Retransmit is performed when
RT is taken HIGH.
when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size
and endian arrangement for Port B. The level of SIZE must be static throughout device operation.
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
This pin muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
TM
WITH
5
CC
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Description
COMMERCIAL TEMPERATURE RANGE