IDT72V3673L10PF IDT, Integrated Device Technology Inc, IDT72V3673L10PF Datasheet - Page 8

• Manufacturer Part Number: IDT72V3673L10PF
• Description: IC SYNCFIFO 8192X36 10NS 128TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3673L10PF

• Function: Asynchronous, Synchronous
• Memory Size: 288K (8K x 36)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3673L10PF

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(For 10ns speed grade only: Vcc = 3.3V
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
4. For 10ns speed grade: Vcc = 3.3V ± 0.15V; T
IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFO
BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S
DH
CLK
CLKH
CLKL
DS
ENS1
ENS2
FSS
BES
SDS
SENS
FWS
ENH
RSTH
FSH
BEH
SDH
SENH
SPH
SKEW1
SKEW2
RSTS
RTMS
RTMH
Symbol
(2)
(2,3)
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑
Setup Time, ENA, and MBA before CLKA↑; ENB and MBB before CLKB↑
Setup Time, RS1 or PRS LOW before CLKA↑ or CLKB↑
Setup Time, FS0, FS1 and FS2 before RS1 HIGH
Setup Time, BE/FWFT before RS1 HIGH
Setup Time, FS0/SD before CLKA↑
Setup Time, FS1/SEN before CLKA↑
Setup Time, FWFT before CLKA↑
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Setup Time, RTM before RT1; RTM before RT2
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB
Hold Time, RS1 or PRS LOW after CLKA↑ or CLKB↑
Hold Time, FS0, FS1 and FS2 after RS1 HIGH
Hold Time, BE/FWFT after RS1 HIGH
Hold Time, FS0/SD after CLKA↑
Hold Time, FS1/SEN HIGH after CLKA↑
Hold Time, FS1/SEN HIGH after RS1 HIGH
Hold Time, RTM after RT1; RTM after RT2
Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR
Skew Time between CLKA↑ and CLKB↑ for AE and AF
after CLKB↑
Parameter
±
A
0.15V
= 0° to +70°.
;
T
A
= 0
ο
TM
C to +70
WITH
ο
(1)
C; JEDEC JESD8-A compliant)
(1)
8
IDT72V3653L10
IDT72V3663L10
IDT72V3673L10
Min.
4.5
4.5
7.5
7.5
0.5
0.5
0.5
0.5
10
12
—
3
4
3
5
3
3
0
5
4
2
2
2
5
5
COMMERCIAL TEMPERATURE RANGE
Max.
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(4)
(4)
(4)
IDT72V3653L15
IDT72V3663L15
IDT72V3673L15
Min.
4.5
4.5
7.5
7.5
7.5
15
12
—
6
6
4
5
4
4
0
1
5
1
4
2
2
1
1
2
5
Max.
66.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns