LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 10

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Figure 15-9.
Figure 15-10. MICROWIRE Frame Format (Single Frame) .................................................................... 423
Figure 15-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 424
Figure 15-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 424
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
Figure 16-10. Master Burst RECEIVE .................................................................................................. 462
Figure 16-11. Master Burst RECEIVE after Burst SEND ........................................................................ 463
Figure 16-12. Master Burst SEND after Burst RECEIVE ........................................................................ 464
Figure 16-13. Slave Command Sequence ............................................................................................ 465
Figure 17-1.
Figure 17-2.
Figure 18-1.
Figure 19-1.
Figure 22-1.
Figure 22-2.
Figure 22-3.
Figure 22-4.
Figure 22-5.
Figure 22-6.
Figure 22-7.
Figure 22-8.
Figure 22-9.
Figure 22-10. Power-On Reset Timing ................................................................................................. 640
Figure 22-11. Brown-Out Reset Timing ................................................................................................ 641
Figure 22-12. Software Reset Timing ................................................................................................... 641
Figure 22-13. Watchdog Reset Timing ................................................................................................. 641
Figure 23-1.
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Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 422
I
I
START and STOP Conditions ......................................................................................... 455
Complete Data Transfer with a 7-Bit Address ................................................................... 456
R/S Bit in First Byte ........................................................................................................ 456
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 459
Master Single RECEIVE ................................................................................................. 460
Master Burst SEND ....................................................................................................... 461
CAN Module Block Diagram ........................................................................................... 490
CAN Bit Time ................................................................................................................ 497
USB Module Block Diagram ........................................................................................... 530
64-Pin LQFP Package Pin Diagram ................................................................................ 618
Load Conditions ............................................................................................................ 633
I
Hibernation Module Timing ............................................................................................. 636
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 637
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 637
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 638
JTAG Test Clock Input Timing ......................................................................................... 639
JTAG Test Access Port (TAP) Timing .............................................................................. 639
External Reset Timing (RST) .......................................................................................... 640
64-Pin LQFP Package ................................................................................................... 642
2
2
2
C Block Diagram ......................................................................................................... 454
C Bus Configuration .................................................................................................... 455
C Timing ..................................................................................................................... 636
Preliminary
2
C Bus ............................................................... 456
June 02, 2008