LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 18

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Inter-Integrated Circuit (I
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Controller Area Network (CAN) Module ..................................................................................... 489
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
18
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 442
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 443
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 444
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 445
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 446
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 447
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 448
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 449
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 450
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 451
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 452
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 453
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CAN Control (CANCTL), offset 0x000 ............................................................................. 502
CAN Status (CANSTS), offset 0x004 ............................................................................... 504
CAN Error Counter (CANERR), offset 0x008 ................................................................... 507
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 508
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 510
CAN Test (CANTST), offset 0x014 .................................................................................. 511
CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 513
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 514
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 514
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 515
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 515
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 518
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 518
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 519
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 519
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 520
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 520
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 468
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 469
C Master Data (I2CMDR), offset 0x008 ......................................................................... 473
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 474
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 475
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 476
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 477
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 478
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 479
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 481
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 482
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 484
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 485
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 486
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 487
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 488
2
C) Interface ........................................................................................ 454
Preliminary
June 02, 2008