LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 495

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

17.4.11
17.4.12
June 02, 2008
Handling of Received Message Objects
The CPU may read a received message any time via the CAN Interface registers because the data
consistency is guaranteed by the message handler state machine.
Typically, the CPU first writes 0x007F to the CAN IFn Command Mask (CANIFnCMSK) register
and then writes the number of the message object to the CAN IFn Command Request
(CANIFnCRQ) register. That combination transfers the whole received message from the message
RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn, and CANIFnMCTL).
Additionally, the NewDat and IntPnd bits are cleared in the message RAM, acknowledging that
the message has been read and clearing the pending interrupt being generated by this message
object.
If the message object uses masks for acceptance filtering, the arbitration bits show which of the
matching messages has been received.
The actual value of NewDat shows whether a new message has been received since the last time
this message object was read. The actual value of MsgLst shows whether more than one message
has been received since the last time this message object was read. MsgLst is not automatically
reset.
Using a remote frame, the CPU may request new data from another CAN node on the CAN bus.
Setting the TxRqst bit of a receive object causes the transmission of a remote frame with the receive
object's identifier. This remote frame triggers the other CAN node to start the transmission of the
matching data frame. If the matching data frame is received before the remote frame could be
transmitted, the TxRqst bit is automatically reset. This prevents the possible loss of data when the
other device on the CAN bus has already transmitted the data slightly earlier than expected.
Handling of Interrupts
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt
with the highest priority, disregarding their chronological order. An interrupt remains pending until
the CPU has cleared it.
The Status Interrupt has the highest priority. Among the message interrupts, the message object's
interrupt priority decreases with increasing message number. A message interrupt is cleared by
clearing the message object's IntPnd bit. The Status Interrupt is cleared by reading the CAN Status
(CANSTS) register.
The interrupt identifier IntId in the CANINT register indicates the cause of the interrupt. When no
interrupt is pending, the register holds the value to 0. If the value of CANINT is different from 0, then
there is an interrupt pending. If the IE bit is set in the CANCTL register, the interrupt line to the CPU
is active. The interrupt line remains active until CANINT is 0, all interrupt sources have been cleared
(the cause of the interrupt is reset), or until IE is reset, which disables interrupts from the CAN
controller.
The value 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN
module has updated, but not necessarily changed, the CANSTS register (Error Interrupt or Status
Interrupt). This indicates that there is either a new Error Interrupt or a new Status Interrupt. A write
access can clear the RxOK, TxOK, and LEC flags in the CANSTS register, however, only a read
access to the CANSTS register will clear the source of the Status Interrupt.
IntId points to the pending message interrupt with the highest interrupt priority. The SIE bit in the
CANCTL register controls whether a change of the status register may cause an interrupt. The EIE
bit in the CANCTL register controls whether any interrupt from the CAN controller actually generates
an interrupt to the microcontroller's interrupt controller. The CANINT interrupt register is updated
even when the IE bit is set to zero.
Preliminary
LM3S5632 Microcontroller
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