LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 578

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Univeral Serial Bus (USB) Controller
USBCSRH0 Host
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
USBCSRH0 Device Mode
USB Control and Status Endpoint 0 High (USBCSRH0)
Base 0x4005.0000
Offset 0x103
Type W1C, reset 0x00
578
Host
Device
Bit/Field
7:3
RO
2
1
0
RO
7
0
7
0
RO
RO
Register 49: USB Control and Status Endpoint 0 High (USBCSRH0), offset
0x103
USBSR0H is an 8-bit register that provides control and status bits for endpoint 0.
6
0
6
0
reserved
RO
RO
reserved
5
0
5
0
FLUSH
DTWE
Name
DT
reserved
RO
RO
4
0
4
0
RO
RO
3
0
3
0
W1C
Type
W1S
R/W
RO
DTWE
W1S
RO
2
0
2
0
R/W
RO
DT
Reset
0x00
1
0
1
0
0
0
0
Preliminary
FLUSH
FLUSH
W1C
W1S
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data Toggle Write Enable
The CPU writes a 1 to this bit to enable the current state of the endpoint
0 data toggle to be written (see DT bit). This bit is automatically cleared
once the new value is written.
Data Toggle
When read, this bit indicates the current state of the endpoint 0 data
toggle. If DTWE is High, this bit may be written with the required setting
of the data toggle. If DTWE is Low, this cannot be written.
Flush FIFO
The CPU writes a 1 to this bit to flush the next packet to be
transmitted/read from the endpoint 0 FIFO. The FIFO pointer is reset
and the TXRDY/RXRDY bit is cleared.
Important:
FLUSH should only be used when TXRDY/RXRDY is set.
At other times, it may cause data to be corrupted.
June 02, 2008