LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 350

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Analog-to-Digital Converter (ADC)
ADC Interrupt Mask (ADCIM)
Base 0x4003.8000
Offset 0x008
Type R/W, reset 0x0000.0000
350
Bit/Field
31:4
RO
RO
3
2
1
0
31
15
0
0
RO
RO
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008
This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller
interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently.
30
14
0
0
RO
RO
29
13
reserved
0
0
MASK3
MASK2
MASK1
MASK0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
26
10
0
0
reserved
RO
RO
Reset
25
0x00
0
9
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 3
(ADCRIS register INR3 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
SS2 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 2
(ADCRIS register INR2 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
SS1 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 1
(ADCRIS register INR1 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
SS0 Interrupt Mask
Specifies whether the raw interrupt signal from Sample Sequencer 0
(ADCRIS register INR0 bit) is promoted to a controller interrupt. If set,
the raw interrupt signal is promoted to a controller interrupt. Otherwise,
it is not.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
MASK3
R/W
RO
19
0
3
0
MASK2
R/W
RO
18
0
2
0
MASK1
R/W
RO
17
0
1
0
June 02, 2008
MASK0
R/W
RO
16
0
0
0