LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 586

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
Univeral Serial Bus (USB) Controller
USBTXCSRHn Host Mode
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1)
Base 0x4005.0000
Offset 0x113
Type R/W, reset 0x00
586
Host
Device
Bit/Field
AUTOSET
R/W
7
6
5
4
7
0
reserved
RO
Register 56: USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1),
offset 0x113
Register 57: USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2),
offset 0x123
Register 58: USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3),
offset 0x133
USBTXCSRHn is an 8-bit register that provides additional control for transfers through the currently
selected transmit endpoint.
6
0
MODE
R/W
AUTOSET
reserved
5
0
DMAEN
MODE
Name
DMAEN
R/W
4
0
FDT
R/W
3
0
Type
R/W
R/W
R/W
RO
DMAMOD
R/W
2
0
DTWE
W1S
Reset
1
0
0
0
0
0
Preliminary
R/W
DT
0
0
Description
Auto Set
If the CPU sets this bit, TXRDY is automatically set when data of the
maximum packet size (value in USBTXMAXPn) is loaded into the
transmit FIFO. If a packet of less than the maximum packet size is
loaded, then TXRDY must be set manually.
Note:
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Mode
The CPU sets this bit to enable the endpoint direction as TX, and clears
it to enable the endpoint direction as RX.
Note:
DMA Request Enable
The CPU sets this bit to enable the DMA request for the transmit
endpoint.
This bit should not be set for either high-bandwidth
isochronous or high-bandwidth interrupt endpoints.
This bit only has an effect when the same endpoint FIFO is
used for both transmit and receive transactions.
June 02, 2008