LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 78

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LM3S5632

Manufacturer Part Number
LM3S5632
Description
Lm3s5632 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Reset
Reset
Type
Type
System Control
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
78
Bit/Field
31:9
5:2
RO
RO
8
7
6
1
0
31
15
0
0
RO
RO
Register 4: Raw Interrupt Status (RIS), offset 0x050
Central location for system control raw interrupts. These are set and cleared by hardware.
30
14
0
0
MOSCPUPRIS
USBPLLLRIS
RO
RO
29
13
reserved
PLLLRIS
reserved
reserved
BORRIS
0
0
Name
reserved
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0
9
0
0
0
0
0
0
0
0
MOSCPUPRIS
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MOSC Power Up Raw Interrupt Status
This bit is set when the PLL T
USB PLL Lock Raw Interrupt Status
This bit is set when the USB PLL T
PLL Lock Raw Interrupt Status
This bit is set when the PLL T
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Brown-Out Reset Raw Interrupt Status
This bit is the raw interrupt status for any brown-out conditions. If set,
a brown-out condition is currently active. This is an unregistered signal
from the brown-out detection circuit. An interrupt is reported if the BORIM
bit in the IMC register is set and the BORIOR bit in the PBORCTL register
is cleared.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USBPLLLRIS
RO
RO
23
0
7
0
PLLLRIS
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
MOSCPUP
READY
0
4
0
reserved
USBREADY
Timer asserts.
RO
RO
19
0
3
0
Timer asserts.
Timer asserts.
RO
RO
18
0
2
0
BORRIS
RO
RO
17
0
1
0
June 02, 2008
reserved
RO
RO
16
0
0
0

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