LM3S5632 Luminary Micro, Inc, LM3S5632 Datasheet - Page 13

• Manufacturer Part Number: LM3S5632
• Description: Lm3s5632 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

List of Registers
System Control .............................................................................................................................. 63
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Hibernation Module ..................................................................................................................... 125
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
June 02, 2008
Device Identification 0 (DID0), offset 0x000 ....................................................................... 74
Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 76
LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 77
Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 78
Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 79
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 80
Reset Cause (RESC), offset 0x05C .................................................................................. 81
Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 82
XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 86
GPIO High Speed Control (GPIOHSCTL), offset 0x06C ..................................................... 87
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 88
Main Oscillator Control (MOSCCTL), offset 0x07C ............................................................. 90
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 91
Device Identification 1 (DID1), offset 0x004 ....................................................................... 92
Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 94
Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 95
Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 97
Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 98
Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 99
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 100
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 101
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 102
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 104
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 106
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 108
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 110
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 112
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 114
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 116
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 118
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 120
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 122
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 123
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 124
Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 135
Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 136
Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 137
Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 138
Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 139
Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 142
Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 143
Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 144
Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 145
Preliminary
LM3S5632 Microcontroller
13