LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 14

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 10:
Register 11:
Internal Memory ........................................................................................................................... 151
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Micro Direct Memory Access (μDMA) ........................................................................................ 180
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
14
Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 149
Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 150
ROM Control (RMCTL), offset 0x0F0 .............................................................................. 157
Flash Memory Address (FMA), offset 0x000 .................................................................... 158
Flash Memory Data (FMD), offset 0x004 ......................................................................... 159
Flash Memory Control (FMC), offset 0x008 ..................................................................... 160
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 162
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 163
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 164
USec Reload (USECRL), offset 0x140 ............................................................................ 165
ROM Version Register (RMVER), offset 0x0F4 ................................................................ 166
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 167
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 168
User Debug (USER_DBG), offset 0x1D0 ......................................................................... 169
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 170
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 171
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 172
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 173
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 174
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 175
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 176
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 177
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 178
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 179
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 202
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 203
DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 204
DMA Status (DMASTAT), offset 0x000 ............................................................................ 208
DMA Configuration (DMACFG), offset 0x004 ................................................................... 210
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 211
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 212
DMA Channel Wait on Request Status (DMAWAITSTAT), offset 0x010 ............................. 213
DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 214
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 215
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 217
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 218
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 220
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 221
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 223
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 224
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 226
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 227
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 229
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 230
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 232
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 233
Preliminary
June 02, 2008