LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 42

• Manufacturer Part Number: LM3S3739
• Description: Lm3s3739 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

ARM Cortex-M3 Processor Core
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A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris
When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value
in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks.
Writing a value of zero to the Reload Value register disables the counter on the next wrap. When
the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write
does not trigger the SysTick exception logic. On a read, the current value is the value of the register
at the time the register is accessed.
If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect
to a reference clock. The reference clock can be the core clock or an external clock source.
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field
31:17
15:3
16
A control and status counter to configure its clock, enable the counter, enable the SysTick
interrupt, and determine counter status.
The reload value for the counter, used to provide the counter's wrap value.
The current value of the counter.
2
1
COUNTFLAG
CLKSOURCE
reserved
reserved
TICKINT
Name
Type
R/W
R/W
R/W
RO
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
Count Flag
Returns 1 if timer counted to 0 since last time this was read. Clears on read by
application. If read by the debugger using the DAP, this bit is cleared on read-only
if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
Software should not rely on the value of a reserved bit. To provide compatibility with
future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
Clock Source
If no reference clock is provided, it is held at 1 and so gives the same time as the
core clock. The core clock must be at least 2.5 times faster than the reference clock.
If it is not, the count values are unpredictable.
Tick Interrupt
Value
0
1
Value
0
1
Preliminary
Description
External reference clock. (Not implemented for Stellaris microcontrollers.)
Core clock
Description
Counting down to 0 does not generate the interrupt request to the NVIC.
Software can use the COUNTFLAG to determine if ever counted to 0.
Counting down to 0 pends the SysTick handler.
June 02, 2008
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devices.