LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 384
LM3S3739
Manufacturer Part Number
LM3S3739
Description
Lm3s3739 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S3739.pdf
(664 pages)
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Universal Asynchronous Receivers/Transmitters (UARTs)
14.4
Table 14-1. UART Register Map
384
0xFDC
Offset
0x02C
0x03C
0xFD0
0xFD4
0xFD8
0xFE0
0x000
0x004
0x018
0x020
0x024
0x028
0x030
0x034
0x038
0x040
0x044
0x048
Name
UARTDR
UARTRSR/UARTECR
UARTFR
UARTILPR
UARTIBRD
UARTFBRD
UARTLCRH
UARTCTL
UARTIFLS
UARTIM
UARTRIS
UARTMIS
UARTICR
UARTDMACTL
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
UARTPeriphID0
5.
6.
Register Map
Table 14-1 on page 384 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■
■
■
Note:
UART0: 0x4000.C000
UART1: 0x4000.D000
UART2: 0x4000.E000
Optionally, configure the uDMA channel (see “Micro Direct Memory Access (μDMA)” on page 180)
and enable the DMA option(s) in the UARTDMACTL register.
Enable the UART by setting the UARTEN bit in the UARTCTL register.
The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 397)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Type
W1C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
0x0000.0000
0x0000.0000
0x0000.0090
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0300
0x0000.0012
0x0000.0000
0x0000.000F
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0011
Reset
Preliminary
Description
UART Data
UART Receive Status/Error Clear
UART Flag
UART IrDA Low-Power Register
UART Integer Baud-Rate Divisor
UART Fractional Baud-Rate Divisor
UART Line Control
UART Control
UART Interrupt FIFO Level Select
UART Interrupt Mask
UART Raw Interrupt Status
UART Masked Interrupt Status
UART Interrupt Clear
UART DMA Control
UART Peripheral Identification 4
UART Peripheral Identification 5
UART Peripheral Identification 6
UART Peripheral Identification 7
UART Peripheral Identification 0
June 02, 2008
page
See
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