LM3S3739 Luminary Micro, Inc, LM3S3739 Datasheet - Page 164
LM3S3739
Manufacturer Part Number
LM3S3739
Description
Lm3s3739 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S3739.pdf
(664 pages)
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Reset
Type
Type
Internal Memory
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
8.7
164
Bit/Field
31:2
RO
RO
1
0
31
15
0
0
RO
RO
Register 7: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
30
14
Flash Register Descriptions (System Control Offset)
The remainder of this section lists and describes the Flash Memory registers, in numerical order by
address offset. Registers in this section are relative to the System Control base address of
0x400F.E000.
0
0
RO
RO
29
13
reserved
0
0
PMISC
AMISC
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
R/W1C
R/W1C
Type
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0
9
0
0x0
reserved
0
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because a
programming cycle completed and was not masked. This bit is cleared
by writing a 1. The PRIS bit in the FCRIS register (see page 162) is also
cleared when the PMISC bit is cleared.
Access Masked Interrupt Status and Clear
This bit indicates whether an interrupt was signaled because an improper
access was attempted and was not masked. This bit is cleared by writing
a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC
bit is cleared.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
PMISC
R/W1C
RO
17
0
1
0
June 02, 2008
R/W1C
AMISC
RO
16
0
0
0
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