IDT723644L12PF IDT, Integrated Device Technology Inc, IDT723644L12PF Datasheet - Page 12

• Manufacturer Part Number: IDT723644L12PF
• Description: IC FIFO SYNC 2048X36 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723644L12PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723644L12PF

impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are
active outputs when both CSA and W/RA are LOW.
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA
is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and
writes on Port A are independent of any concurrent Port B operation.
that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read
select (W/RA). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-B35
lines are in the high-impedance state when either CSB is HIGH or W/RB is
LOW. The B0-B35 lines are active outputs when CSB is LOW and W/RB is
HIGH.
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is
LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs
by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB
is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO reads and
writes on Port B are independent of any concurrent Port A operation.
and Write/Read selects are only for enabling write and read operations and
are not related to high-impedance control of the data outputs. If a port enable
TABLE 2 — PORT A ENABLE FUNCTION TABLE
TABLE 3 — PORT B ENABLE FUNCTION TABLE
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CSA
CSB
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
The Port B control signals are identical to those of Port A with the exception
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
The setup and hold time constraints to the port clocks for the port Chip Selects
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
W/RA
W/RB
H
H
H
X
L
L
L
L
H
H
H
H
X
L
L
L
ENA
ENB
H
H
H
H
H
H
H
H
X
L
L
L
X
L
L
L
MBA
MBB
H
H
H
H
H
H
X
X
L
L
L
X
X
L
L
L
CLKA
CLKB
X
X
↑
↑
X
↑
X
↑
↑
↑
↑
↑
X
X
X
X
Data A (A0-A35) I/O
Data B (B0-B35) I/O
High-Impedance
High-Impedance
12
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
the Empty Flag to change state on the second LOW-to-HIGH transition of the
Read clock. The data word will not be automatically sent to the output register.
Instead, data residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select. Write and Read timing diagrams for Port
A can be found in Figure 7 and 14. Relevant Port B Write and Read cycle timing
diagrams together with Bus-Matching and Endian select operations can be
found in Figures 8 through 13.
SYNCHRONIZED FIFO FLAGS
stages. This is done to improve flag-signal reliability by reducing the probability
of metastable events when CLKA and CLKB operate asynchronously to one
another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
When operating the FIFO in FWFT mode and the Output Ready flag is LOW,
When operating the FIFO in IDT Standard mode, the first word will cause
Each FIFO is synchronized to its port clock through at least two flip-flop
COMMERCIAL TEMPERATURE RANGE
Mail2 read (set MBF2 HIGH)
Mail1 read (set MBF1 HIGH)
PORT FUNCTION
PORT FUNCTION
FIFO1 write
FIFO2 read
Mail1 write
FIFO2 write
FIFO1 read
Mail2 write
None
None
None
None
None
None
None
None