IDT723644L12PF IDT, Integrated Device Technology Inc, IDT723644L12PF Datasheet - Page 23

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IDT723644L12PF

Manufacturer Part Number
IDT723644L12PF
Description
IC FIFO SYNC 2048X36 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT723644L12PF

Function
Synchronous
Memory Size
72K (2K x 36)
Data Rate
83MHz
Access Time
12ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
723644L12PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT723644L12PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT723644L12PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
If the time between the rising CLKA edge and rising CLKB edge is less than t
cycle later than shown.
SKEW1
A0-A35
B0-B35
CLKA
CLKB
W/RB
WRA
MBA
MBB
CSA
ENA
ORB
ENB
CSB
IRA
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
FIFO1 Empty
HIGH
LOW
HIGH
LOW
HIGH
LOW
Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
t
t
ENS2
ENS2
t
DS
W1
Old Data in FIFO1 Output Register
t
SKEW1
t
t
ENH
t
ENH
DH
(1)
t
CLKH
1
t
CLK
SKEW1
t
CLKL
, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
23
2
t
CLKH
t
CLK
t
CLKL
t
REF
3
t
A
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
REF
t
ENH
W1
3270 drw17

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