IDT723644L12PF IDT, Integrated Device Technology Inc, IDT723644L12PF Datasheet - Page 3

• Manufacturer Part Number: IDT723644L12PF
• Description: IC FIFO SYNC 2048X36 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723644L12PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723644L12PF

mailbox registers. The mailbox register width matches the selected Port B bus
width. Each Mailbox register has a flag (MBF1 and MBF2) to signal when new
mail has been stored.
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array, configures the FIFO for Big- or Little-Endian byte
arrangement and selects serial flag programming, parallel flag programming,
or one of three possible default flag offset settings, 8, 16 or 64. There are two
Master Reset pins, MRS1 and MRS2.
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2.
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation is required (nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/FWFT pin
during FIFO operation determines the mode in use.
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/IRB).
The EF and FF functions are selected in the IDT Standard mode. EF indicates
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Communication between each port may bypass the FIFOs via two
Two kinds of reset are available on these FIFOs: Master Reset and Partial
Partial Reset also sets the read and write pointers to the first location of the
These devices have two modes of operation: In the IDT Standard mode,
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and
3
whether or not the FIFO memory is empty. FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
a programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate when
a selected number of words remain in the FIFO memory. AFA and AFB indicate
when the FIFO contains more than a selected number of words.
clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are
two-stage synchronized to the port clock that reads data from its array.
Programmable offsets for AEA, AEB, AFA and AFB are loaded in parallel using
Port A or in serial via the SD input. The Serial Programming Mode pin (SPM)
makes this selection. Three default offset settings are also provided. The AEA
and AEB threshold can be set at 8, 16 or 64 locations from the empty boundary
and the AFA and AFB threshold can be set at 8, 16 or 64 locations from the full
boundary. All these choices are made using the FS0 and FS1 inputs during
Master Reset.
paths. If, at any time, the FIFO is not actively performing a function, the chip
will automatically power down. During the power down state, supply current
consumption (I
control inputs) will immediately take the device out of the power down state.
0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available. They
are fabricated using IDT’s high speed, submicron CMOS technology.
The IDT723624/723634/723644 are characterized for operation from
Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port
Two or more devices may be used in parallel to create wider data
CC
) is at a minimum. Initiating any operation (by activating
COMMERCIAL TEMPERATURE RANGE