IDT723644L12PF IDT, Integrated Device Technology Inc, IDT723644L12PF Datasheet - Page 8

• Manufacturer Part Number: IDT723644L12PF
• Description: IC FIFO SYNC 2048X36 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723644L12PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 83MHz
• Access Time: 12ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723644L12PF

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: V
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTES:
1. Industrial temperature range is available by special order.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S
DH
CLK
CLKH
CLKL
DS
ENS1
ENS2
FSS
BES
SPMS
SDS
SENS
FWS
ENH
RSTH
FSH
BEH
SPMH
SDH
SENH
SPH
SKEW1
SKEW2
RSTS
(3)
(3,4)
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑
Setup Time ENA and MBA before CLKA↑; ENB and MBB before CLKB↑
Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA↑ or CLKB↑
Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH
Setup Time, BE/FWFT before MRS1 and MRS2 HIGH
Setup Time, SPM before MRS1 and MRS2 HIGH
Setup Time, FS0/SD before CLKA↑
Setup Time, FS1/SEN before CLKA↑
Setup Time, BE/FWFT before CLKA↑
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and MBB
after CLKB↑
Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA↑ or CLKB↑
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
Hold Time, SPM after MRS1 and MRS2 HIGH
Hold Time, FS0/SD after CLKA↑
Hold Time, FS1/SEN HIGH after CLKA↑
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
Skew Time between CLKA↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB
Skew Time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
CC
= 5V ± 10%, T
Parameter
A
= 0°C to +70°C)
8
(2)
(2)
COMMERCIAL TEMPERATURE RANGE
IDT723624L12 IDT723624L15
IDT723634L12 IDT723634L15
IDT723644L12 IDT723644L15
Min.
7.5
7.5
7.5
0.5
0.5
0.5
0.5
—
12
12
5
5
3
4
3
5
3
3
0
4
2
2
2
2
5
Commercial
Max.
83
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.5
4.5
7.5
7.5
7.5
7.5
Min.
15
12
—
6
6
4
5
4
4
0
1
1
4
2
2
2
1
1
2
Max.
66.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns